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bcrtmp-1 ut1553 bcrtmp f e a t u r e s p comprehensive mil-std-1553 dual-redundant bus controller (bc) and remote terminal (rt) functions p multiple message processing capability in bc and rt modes p time tagging and message logging in rt mode p automatic polling and intermessage delay in bc mode p programmable interrupt scheme and internally generated interrupt history list p remote terminal operations in asd/enasd-certified (seafac) p register-oriented architecture to enhance programmability p dma memory interface with 64k addressability p eight mode select inputs configure the device for a wide variety of 1553 protocols: mil-std-1553a, mil-std-1553b, mcdonnell douglas a3818, a5232, a5690, grumman aerospace sp-g-151a p comprehensive built-in-test (bit) includes: continuous on-line wrap-around test, off-line bit, special system wrap-around test p available in 144-pin pingrid array or 132-lead flatpack packages p standard microcircuit drawing 5962-89501 available - qml q compliant 16 16 16 control dma/cpu message rt protocol message bc protocol handler interrupt conver- parallel serial-to- conver- to-serial parallel- module decoder encoder/ channel dual bus transfer logic address 16 timeout timrona clock & reset 12mhz master reset generator address 16 1553 high-priority rt address standard interrupt high-priority interrupt log current command built-in-test word polling compare current bc block/ status control registers list pointer data 16 built- in- test 16 16 rt timer interrupt status interrupt enable sion sion & handler & handler data channel b 1553 data channel a logic high-priority std priority level std priority pulse dma arbitration register control dual-port memory control rt descriptor space enable built-in-test start command reset command reset command activity status/ operational mode programmable status w r a p - a r o u n d t e s t m u l t i p l e x e r timronb figure 1. bcrtmp blockdiagram
bcrtmp -2 table of contents 1.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features - remote terminal (rt) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 features - bus controller (bc) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 features - multiple protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.0 pin identification and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.0 internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0 system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.0 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 hardware interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 cpu interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4 ram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.5 legalization bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6 transmitter/receiver interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.0 remote terminal architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 rt functional operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1.1 rt subaddress descriptor definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1.2 message status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.3 mode code descriptor definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2 rt error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3 rt operational sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.0 bus controller architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 bc functional operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2 polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3 bc error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.4 bc operational sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.5 bc operational example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.0 multiple protocol options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1 operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1.1 legalization select (rt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1.2 broadcast option select (bc, rt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1.3 rt response time select (rt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1.4 mode code option select (bc, rt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1.5 status word option select (rt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1.6 message error technique select (rt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1.7 mode code with data select (bc, rt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1.8 remote terminal time out option select (bc, rt) . . . . . . . . . . . . . . . . . . 43 8.2 additional ut1553 bcrtmp features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.2.1 domc do mode code control signal (rt) . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.2.2 continuous wrap-around circuitry (bc, rt) . . . . . . . . . . . . . . . . . . . . . . . 44 8.2.3 stop enable (bc, rt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.2.4 forced busy (rt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.2.5 active signal (rt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.2.6 transmitter inhibit signals (bc, rt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.2.7 immediate clear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.2.8 status word generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.0 exception handling and interrupt logging . . . . . . . . . . . . . . . . . . . . 46 10.0 maximum and recommended operating conditions . . . . . . . . . . . . 50 11.0 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.0 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.0 package outline drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
bcrtmp-3 1.0 i n t r o d u c t i o n the monolithic cmos ut1553 bcrtmp provides the system designer with an intelligent solution to mil-std-1553 multiplexed serial data bus design problems. the ut1553 bcrtmp is a single-chip device that implements two of the three defined mil-std-1553 functions - bus controller and remote terminal - and is flexible enough to conform to many of the mil-std-1553 ?industry standards? created between and including releases of mil-std-1553a and mil-std-1553b. designed to reduce host cpu overhead, the bcrtmp?s powerful state machines automatically execute message transfers, provide interrupts, and generate status information. the bcrtmp?s register-based architecture allows it to conform to the many protocol options regarding status words, mode codes, use of broadcast, message error, and rt response time as specified in the various ?1553 standards.? multiple registers offer many programmable functions as well as extensive information for host use. in the bc mode, the bcrtmp uses a linked-list message scheme to provide the host with message chaining capability. the bcrtmp enhances memory use by supporting variable-size, relocatable data blocks. in the rt mode, the bcrtmp implements time- tagging and message history functions. it also supports multiple (up to 128) message buffering and variable length messages to any subaddress. the ut1553 bcrtmp is an intelligent, versatile, and easy to implement device -- a powerful asset to system designers. 1.1 features - remote terminal (rt) mode indexing the bcrtmp is programmable to index or buffer messages on a subaddress-by-subaddress basis. the bcrtmp, which can index as many as 128 messages, can also assert an interrupt when either the selected number of messages is reached or every time a specified subaddress is accessed. variable space allocation the bcrtmp can use as little or as much memory (up to 64k) as needed. selectable data storage address programmability within the bcrtmp provides flexible data placement and convenient access. sequential data storage the bcrtmp stores/retrieves, by subaddress, all messages in the order in which they are transacted. sequential message status information the bcrtmp provides message validity, time-tag, and word-count information, and stores it sequentially in a separate, cross-referenced list. illegalizing mode codes and subaddresses the host can declare mode codes and subaddresses illegal by setting the appropriate bit(s) in memory. programmable interrupt selection the host cpu can select various events to cause an interrupt with provision for high and standard priority interrupts. interrupt history list the bcrtmp provides an interrupt history list that records, in the order of occurrence, the events that caused the interrupts. the list length is programmable. 1.2 features - bus controller (bc) mode multiple message processing the bcrtmp autonomously processes any number of messages or lists of messages that may be stored in a 64k memory space. automatic intermessage delay when programmed by the host, the bcrtmp can delay a host-specified time before executing the next message in sequence. automatic polling when polling, the bcrtmp interrogates the remote terminals and then compares their status word responses to the contents of the polling compare register. the bcrtmp can interrupt the host cpu if an erroneous remote terminal status word response occurs. automatic retry the bcrtmp can automatically retry a message on busy, message error, and/or response time-out conditions. the bcrtmp can retry up to four times on the same or on the alternate bus. programmable interrupt selection the host cpu can select various events to cause an interrupt with provision for high and standard priority interrupts. interrupt history list the bcrtmp provides an interrupt history list that records, in the order of occurrence, the events that caused the interrupts. the list length is programmable. variable space allocation the bcrtmp uses as little or as much memory (up to 64k) as needed. selectable data storage address programmability within the bcrtmp provides flexible data placement and convenient access.
bcrtmp-4 1.3 features - multiple protocol since the inception of the loosely defined mil-std-1553a in 1973, various ?1553 standards? have developed, all with their own peculiarities. the ut1553 bcrtmp addresses mil-std-1553a, mil-std-1553b, mcdonnell douglas a3818, mcdonnell douglas a5232, mcdonnell douglas a5690, and grumman aerospace sp-g-151a. while the part was designed with these ?standards? specifically in mind, the bcrtmp?s flexibility permits conformance to nearly any conceivable ?1553-like standard.? the basic differences among the various ?standards? fall into five categories: 1) status word definition 2) mode code definition 3) use of broadcast 4) message error handling 5) remote terminal (rt) response time status word definition the bcrtmp can operate in a mode where the status word is defined in strict conformance with mil-std-1553b, or it can operate in a more flexible mode. in this flexible status word mode, the user can program the individual status word bits using internal registers. mode code definition the designer can place the bcrtmp in an operational mode so that the device performs in strict conformance with the mode code definitions for mil-std-1553b. the designer may also opt not to automatically execute mode codes, providing flexibility in mode code definition and illegalization. use of broadcast the bcrtmp has a programmable mode option that allows the user to determine whether to allow broadcast commands in a system. message error handling some 1553 protocols (e. g., mil-std-1553b) consider any message error reason to discard the entire message and suppress status word transmission, while others (e. g., mcdonnell douglas a3818) define the required activity according to message error severity. the bcrtmp can be programmed to conform to either requirement. remote terminal (rt) response time the bcrtmp offers two methods of legalization (bus legalization and dma legalization), which the designer selects depending on the required rt response time.
bcrtmp-5 busyack figure 2. bcrtmp functional pin description d0 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 lgl0 lgl1 lgl2 lgl3 lgl4 lgl5 lgl6 lgl7 lgl8 lgl9 lgl10 raz rao rbz rbo taz tao tbz tbo rta0 rta1 rta2 rta3 rta4 rtpty md7 md6 md5 md4 md3 md2 md1 md0 mdo6 mdo5 mdo4 mdo3 mdo2 mdo1 mdo0 mclk mclkd2 clk vdd vdd vdd vdd vss vss vss vss wrapen wrapf altwrap fbusy dmar dmag dmago dmack burst tsctl brdcast mc lglen lglcmd err domc stdintl stdintp hpint timrona timronb comstr ssysf bcrtf cha/ b test rd wr cs aen bcrtsel lock extovr mrst memcso memcs i rrd rwr data lines ++ d1 d2 d3 ++ ++ ++ ++ address lines + mode outputs* mode select inputs** clock signals power ground wrap-around test signals forced busy signals dma signals legalization bus* legalization signals control signals status signals terminal address** biphase in biphase out + + ** ** ** + + * pin at high impedance when mrst is low. ** pin internally pulled up. + pin at high impedance when not asserted. ++ bidirectional pin. *** formerly memwin . ( ) pingrid array pin identification in parentheses. flatpack pin numbers not in parentheses. active 2.0 p i n i d e n t i f i c a t i o n a n d d e s c r i p t i o n 24 25 26 27 28 29 30 31 36 37 38 39 40 41 42 43 91 92 93 94 95 96 97 102 103 104 105 106 107 108 109 110 23 22 21 20 19 18 17 16 (n6) (p6) (p7) (n7) (r6) (r7) (p8) (r8) (r9) (r10) (p9) (p10) (n10) (r11) (r12) (r13) 14 13 12 11 10 9 8 58 74 3 132 34 67 100 1 33 66 99 6 5 4 (b10) (b9) (c9) (a10) (a9) (b8) (a8) (a7) (a6) (b7) (b6) (c6) (a5) (a4) (a3) (b4) (r4) (p5) (r3) (n5) (p4) (p3) (p2) (n3) (p1) (n2) (l3) (m2) (n1) (m1) (l1) (k14) (e15) (j1) (h3) (n9) (g13) (c7) (j3) (n8) (h13) (c8) (k2) (j2) (k1) (l13) (m14) (k13) (m15) 53 52 57 56 51 50 55 54 44 45 46 47 48 49 82 83 84 85 86 81 90 128 129 89 59 62 63 61 60 87 15 88 7 69 64 70 71 122 123 127 124 125 126 111 112 113 114 115 116 117 118 119 120 121 72 73 78 75 77 76 79 80 (n14) (p14) (l14) (n15) (p12) (n11) (p13) (r14) (n12) (n13) (c13) (b14) (b13) (b12) (c11) (d13) (c10) (g1) (h2) (a12) (j14)*** (j15) (h14) (k15) (j13) (a13) (m3) (b11) (k3) (g15) (h15) (f15) (g14) (d1) (f3) (f1) (f2) (g2) (g3) (c5) (b3) (a2) (c4) (c3) (b2) (c2) (d2) (e3) (c1) (e2) (f14) (f13) (e13) (d15) (d14) (c15) (c14) (b15) **
bcrtmp-6 a0 24 r13 ttb bit 0 (lsb) of the address bus a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 25 26 27 28 29 30 31 36 37 38 39 r12 r11 n10 p10 p9 r10 r9 r8 p8 r7 r6 ttb ttb ttb bit 1 of the address bus bit 2 of the address bus bit 3 of the address bus bit 4 of the address bus bit 5 of the address bus bit 6 of the address bus bit 7 of the address bus bit 8 of the address bus bit 9 of the address bus bit 10 of the address bus bit 11 of the address bus 40 n7 a13 a14 41 42 p7 p6 tto tto tto name pin number f/p pga type active description a15 43 n6 tto tto tto tto tto tto tto tto tto bit 12 of the address bus bit 13 of the address bus bit 14 of the address bus bit 15 (msb) of the address bus -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- legend for type and active fields: tui = ttl input (pull-up) al = active low ah = active high zl = active low - inactive state is high impedance ti = ttl input to = ttl output tto = three-state ttl output ttb = bidirectional notes: 1. address and data buses are in the high-impedance state when idle. 2. flatpack pin numbers are same as lcc. address bus
bcrtmp-7 ttb ttb ttb ttb d0 d1 d2 d3 91 b10 92 93 94 b9 c9 a10 bit 0 (lsb) of the data bus bit 1 of the data bus bit 2 of the data bus bit 3 of the data bus d4 d5 d6 d7 d8 d9 d10 d11 95 96 97 102 103 104 105 106 a9 b8 a8 a7 a6 b7 b6 c6 ttb ttb ttb ttb ttb ttb ttb ttb bit 4 of the data bus bit 5 of the data bus bit 6 of the data bus bit 7 of the data bus bit 8 of the data bus bit 9 of the data bus bit 10 of the data bus bit 11 of the data bus -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- name type active description data bus d12 d13 d14 d15 107 108 109 110 a5 a4 a3 b4 ttb ttb ttb ttb bit 12 of the data bus bit 13 of the data bus bit 14 of the data bus bit 15 (msb) of the data bus -- -- -- -- pin number f/p pga name type active description rta0 terminal address inputs 44 p12 tui remote terminal address bit 0 (lsb). the entire rt address is strobed in at master reset. verify it by reading the remote terminal address register. all the remote terminal address bits are internally pulled up. rta1 45 n11 tui remote terminal address bit 1. this is bit 1 of the remote terminal address. rta2 46 p13 tui remote terminal address bit 2. this is bit 2 of the remote terminal address. rta3 47 r14 tui remote terminal address bit 3. this is bit 3 of the remote terminal address. -- -- -- -- rtpty 49 n13 tui remote terminal (address) parity. this is an odd parity input for the remote terminal address. rta4 48 n12 tui remote terminal address bit 4. this is bit 4 (msb) of the remote terminal address. -- -- pin number f/p pga
bcrtmp-8 61 62 63 k15 j15 h14 ti ti ti al al al aen 60 j13 ti ah bcrtsel 87 a13 tui -- lock 15 88 m3 b11 tui tui ah al 7 k3 al name type active description control signals 69 64 g15 h15 to tui al al 71 g14 to al 70 f15 to al ti read. the host uses this in conjunction with cs to read an internal bcrt register. write. the host uses this in conjunction with cs to write an internal bcrtmp register. bc/ rt select. this selects between either the bus controller or remote terminal mode. the bc/ rt mode select bit in the control register overrides this input if the lock pin is not high. this pin is internally pulled high. lock. when set, this pin prevents internal changes to the rt address and bc/ rt mode select functions as well as the operation mode select (md7-md0) functions. this pin is internally pulled high. external override. use this in multi-redundant applications. upon receipt, the bcrtmp aborts all current activity. extovr should be connected to comstr output of the adjacent bcrtmp when used. this pin is internally pulled high. memory chip select out. this is the regenerated memcsi input for external ram during the pseudo- dual-port ram mode. the bcrtmp also uses it to select external memory during memory accesses. rd wr cs extovr mrst memcso memcsi rrd rwr memory chip select in. used in the pseudo-dual-port ram mode only, memcsi is received from the host and is propagated through to the memcso . this pin is internally pulled high. ram read. in the pseudo-dual-port ram mode, the host uses this signal in conjunction with memcso to read from external ram through the bcrtmp. it is also the signal the bcrtmp uses to read from memory. it is asserted following receipt of dmag . when the bcrtmp performs multiple reads, this signal is pulsed. ram write. in the pseudo-dual-port ram mode, the cpu and bcrtmp use this to write to external ram. this signal is asserted following receipt of dmag . for multiple writes, this signal is pulsed. pin number f/p pga chip select. this selects the bcrtmp when accessing the bcrtmp?s internal register. address enable. the host cpu uses aen to indicate to the bcrtmp that the bcrtmp?s address lines can be asserted; this is a precautionary signal provided to avoid address bus crash. if not used, it must be tied high. master reset. this resets all internal state machines, encoders, decoders, and registers. the minimum pulse width for a successful master reset is 500ns.
bcrtmp-9 82 83 84 c13 b14 b13 tto to tto zl al zl name type active description 85 89 90 b12 a12 c10 to to to al al ssysf bcrtf test 128 129 59 g1 h2 j14 ti to to ah ah al status signals timer on - channel a. when low, this pin indicates that the bcrtmp is transmitting data. this output remains active until the data transmission is complete or until the internal fail-safe timer times out (at 660 m s), indicating that the transceiver should be disabled. 86 c11 to al active 81 d13 to ah activity on 1553 bus. when high, this pin indicates that the bcrtmp has detected a valid command to any remote terminal address on the bus. -- standard interrupt level. this is a level interrupt. it is asserted when one or more events enabled in either the standard interrupt enable register, rt descriptor, or bc command block occur. resetting the standard interrupt bit in the high-priority interrupt status/reset register clears the interrupt. stdintl stdintp standard interrupt pulse. stdintp pulses when an interrupt is logged. hpint high priority interrupt. the high-priority interrupt level is asserted upon occurance of events enabled in the high priority interrupt enable register. the corresponding bit(s) in the high-priority interrupt status/reset register reset hpint. timrona timronb timer on - channel b. see timrona description. comstr cha/ b channela/ b . this indicates the active or last active channel. test. this pin is used as a factory test pin. (formerly memwin .) pin number f/p pga (rt) command strobe. the bcrtmp asserts this signal after receiving a valid command. the bcrtmp deactivates it after servicing the command. subsystem fail. upon receipt, this signal propagates directly to the rt 1553 status word and the bcrtmp status register. bcrt fail. this indicates a built-in-test (bit) failure. in the rt mode, the terminal flag bit in 1553 status word is also set.
bcrtmp-10 name type active description biphase inputs rao 50 p14 ti receive channel a one. this is the manchester-encoded true signal input from channel a of the bus receiver. rbo 54 n15 ti receive channel b one. this is the manchester-encoded true signal input from channel b of the bus receiver. raz rbz 51 55 n14 l14 ti ti receive channel a zero. this is the manchester-encoded complementary signal input from channel a of the bus receiver. receive channel b zero. this is the manchester-encoded complementary signal input from channel b of the bus receiver. -- -- -- -- pin number f/p pga name type active description tao 52 m14 to taz 53 l13 to tbo 56 m15 to -- -- -- tbz 57 k13 to -- biphase outputs transmit channel a one. this is the manchester- encoded true output to be connected to the channel a bus transmitter input. this signal is idle low. transmit channel a zero. this is the manchester- encoded complementary output to be connected to the channel a bus transmitter input. this signal is idle low. transmit channel b one. this is the manchester- encoded true output to be connected to the channel b bus transmitter input. this signal is idle low. transmit channel b zero. this is the manchester- encoded complementary output to be connected to the channel b bus transmitter input. this signal is idle low. pin number f/p pga
bcrtmp-11 72 f14 zl 73 78 75 f13 e13 d15 al al zl tto ti tto to name type active description dma signals 76 c15 to al burst 77 d14 to ah dma request. the bcrtmp issues this signal when access to ram is required. it goes inactive after receiving a dmag signal. dmar dmag dmago dmack tsctl dma grant out. if dmag is received but not needed, it passes through to this output. dma acknowledge. the bcrtmp asserts this signal to confirm receipt of dmag , it stays low until memory access is complete. pin number f/p pga dma grant. this input to the bcrtmp allows the bcrmtp to access ram. it is recognized 45ns before the rising edge of mclkd2. three-state control. this signal indicates when the bcrtmp is actually accessing memory. the host subsystem?s address and data lines must be in the high- impedance state when the signalis active. this signal assists in placing the external data and address buffers into the high- impedance state. burst (dma cycle). this indicates that the current dma cycle transfers at least two words; worst-case is five words plus a ?dummy? word.
bcrtmp-12 mode select inputs name pin number type active description f/p pga md7 23 r4 tui -- mode 7. this input selects between two remote terminal time out (rto) options. when this signal is high, the selected rto is 16 m s. when this signal is low, the selected rto is 32 m s. md6 22 p5 tui -- mode 6. this input selects whether mode codes with data are allowed in the selected 1553 protocol. when this signal is high, the protocol does allow mode codes with data. when this signal is low, the protocol does not allow mode codes with data. md5 21 r3 tui -- mode 5. this input selects the message error handling technique. when this signal is high, the message error handling technique is as defined in mil-std-1553b. when the signal is low, the message error handling technique is as defined in macair a3818. md4 20 n5 tui -- mode 4. this input selects between mil-std-1553a and mil-std-1553b status word protocol. when this signal is high, the selected status word protocol is the ?b? option. when this signal is low, the selected status word protocol is the ?a? option. md3 19 p4 tui -- mode 3. this input selects between mil-std-1553a and mil-std-1553b mode code protocol. when this signal is high, the selected mode code protocol is the ?b? option. when this signal is low, the selected mode code protocol is the ?a? option. md2 18 p3 tui -- mode 2. this input selects between mil-std-1553a and mil-std-1553b rt response time protocol. when this signal is high, the selected response time protocol is the ?b? option. this signal is low, the selected response time protocol is the ?a? option. md1 17 p2 tui -- mode 1. this input selects whether broadcast is allowed. when this signal is high, broadcast is allowed. when this signal is low, broadcast is not allowed. when md1 is low, rt address 11111 is treated like rt addresses 00000-11110. md0 16 n3 tui -- mode 0. this input selects the legalization method. when this signal is high, the dma method of legalization is used. when this signal is low, the legalization bus is used.
bcrtmp-13 mode outputs name pin number type active description f/p pga md06 14 p1 tto -- mode 6 out. this output signal reflects the internal state of mode 6 (md6). mdo5 13 n2 tto -- mode 5 out. this output signal reflects the internal state of mode 5 (md5). mdo4 12 l3 tto -- mode 4 out. this output signal reflects the internal state of mode 4 (md4). mdo3 11 m2 tto -- mode 3 out. this output signal reflects the internal state of mode 3 (md3). mdo2 10 n1 tto -- mode 2 out. this output signal reflects the internal state of mode 2 (md2). mdo1 9 m1 tto -- mode 1 out. this output signal reflects the internal state of mode 1 (md1). md00 8 l1 tto -- mode 0 out. this output signal reflects the internal state of mode 0 (md0). forced busy signal name pin number type active description f/p pga fbusy 79 c14 tui al forced busy. this signal places the rt in a mode where it will automatically respond to a command with the busy bit set in the rt status word. no dma memory bus accesses are necessary, and the memory buses remain in the high-impedance state until the busy mode is exited. if the rt is involved in a 1553 message transaction then entry into the busy state is held off until completion of the last dms associated with that message. upon entry into the busy state, the bcrtmp asserts the busyack signal. busyack 80 n2 tto -- busy acknowledge. this signal indicates that the bcrtmp has entered the forced busy state.
bcrtmp-14 wrap-around test signals name pin number type active description f/p pga wrapen 6 k2 tui al wrap-around enable. when this signal is low, the continuous wrap-around feature is enabled. wrapf 5 j2 to ah wrap fail. when high, this pin indicates that the continuous wrap-around circuitry has detected a failure. altwrap 4 k1 tui al alternate wrap-around. this signal, when used in conjunction with wrapen , places the bcrtmp in a special system diagnostic mode, where the two 1553 buses are connected by a stub, and commands transmitted over one bus are received through the continuous wrap circuitry on the other bus. this permits off-line testing of both channels and the associated 1553 interface components. legalization bus name pin number type active description f/p pga lgl10 121 e2 tto -- legalization bus bit 10. the legalization bus bits 0- 10 reflect bit times 19-9 of the current command (i.e., lgl10 = current command bit time 9 and lgl0 = current command bit time19. this bus is used to determine whether or not the command is legal. this bus can also be used to selectively determine if auto- execution of a particular mode code is allowed. lgl9 120 c1 tto -- legalization bus bit 9 lgl8 119 e3 tto -- legalization bus bit 8 lgl7 118 d2 tto -- legalization bus bit 7 lgl6 117 c2 tto -- legalization bus bit 6 lgl5 116 b2 tto -- legalization bus bit 5 lgl4 115 c3 tto -- legalization bus bit 4. when the macair a3818 method of error logging is selected, legalization bus bits 4-0 reflect the word count for the defective data word. lgl3 114 c4 tto -- legalization bus bit 3 lgl2 113 a2 tto -- legalization bus bit 2 lgl1 112 b3 tto -- legalization bus bit 1 lg10 111 c5 tto -- legalization bus bit 0
bcrtmp-15 name type active description clk mclk mclkd2 3 58 74 j1 k14 e15 ti ti to memory clock divided by two. this signal is the memory clock input divided by two. it assists the host subsystem in synchronizing dma events. clock. the 12mhz input clock requires a 50% 10% duty cycle with an accuracy of 0.01%. the accuracy is required in order to meet the manchester encoding/decoding requirements of mil-std-1553. memory clock. this is the input clock frequency the bcrtmp uses for memory accesses. the memory cycle time is equal to two mclk cycles. therefore, ram access time is dependent upon the chosen mclk frequency (6mhz minimum, 12mhz maximum). please see the bcrtmp dma timing diagrams in this data sheet. -- -- -- clock signals pin number f/p pga legalization signals name pin number type active description f/p pga brdcast 122 d? tto ah broadcast. when high, this pin indicates that the current command is a broadcast command. mc 123 f3 tto ah mode code. when high, this pin indicates that the current command is a mode command. lglen 127 f1 tto al legalization bus enable. when low, this pin enables the user-supplied legalization logic (if the legalization bus is used). lglcmd 124 f2 tui ah legal command. a high on this input signal indicates to the bcrtmp that the current command is legal. err 125 g2 to al error. when low, this pin indicates that a data word parity error or a manchester error occurred in the current command. when this signal is asserted, the legalization bus bits 4-0 contain the word count for the defective data word. domc 126 g3 tui ah do mode code. when high, this signal enables the automatic execution of mode codes. when low, this signal disables auto-execution.
bcrtmp-16 name type active description 132 34 67 100 1 33 66 99 h3 n9 g13 c7 j3 n8 h13 c8 pwr pwr pwr pwr gnd gnd gnd gnd +5v +5v +5v +5v ground ground ground ground -- -- -- -- -- -- -- -- power and v dd v ss v dd v dd v dd v ss v ss v ss pin number f/p pga
bcrtmp-17 3.0 i n t e r n a l r e g i s t e r s the bcrtmp?s internal registers (see table 1 on pages 24- 25) enable the cpu to control the actions of the bcrtmp while maintaining low dma overhead by the bcrtmp. all functions are active high and ignored when low unless stated otherwise. functions and parameters are used in both rt and bc modes except where indicated. registers are addressed by the binary equivalent of their decimal number. for example, register 1 is addressed as 0001b. register usage is defined as follows: #0 control register bit number description bits 15-13 reserved. bit 12 (bc,rt) md7 (mode 7). remote terminal time-out option select. when high, this bit selects a remote terminal time-out that is nominally 32 m s. when low, this bit selects a remote terminal time-out that is nominally 16 m s. bit 11 enable external override. for use in multi-redundant systems. this bit enables the extovr pin. bit 10 bc/ rt select. this function selects between the bus controller and remote terminal operation modes. it overrides the external bcrtsel input setting if the change lock-out function is not used. a reset operation must be performed when changing between bc and rt modes. this bit is write-only. bit 9 (bc) retry on alternate bus. this bit enables an automatic retry to operate on alternate buses. for example, if on bus a, with two automatic retries programmed, the automatic retries occur on bus b. bit 8 (rt) channel b enable. when set, this bit enables channel b operation. (bc) no significance. bit 7 (rt) channel a enable. when set, this bit enables channel a operation. (bc) channel select a/ b . when set, this bit selects channel a. bits 6-5 (bc) retry count. these bits program the number (1-4) of retries to attempt. (00 = 1 retry, 11 = 4 retries) bit 4 (bc) retry on bus controller message error. this bit enables automatic retries on an error the bus controller detects (see the bus controller architecture section, page 36). bit 3 (bc) retry on time-out. this bit enables an automatic retry on a response time-out condition. bit 2 (bc) retry on message error. this bit enables an automatic retry when the message error bit is set in the rt?s status word response. bit 1 (bc) retry on busy. this bit enables automatic retry on a received busy bit in an rt status word response. bit 0 start enable. in the bc mode, this bit starts/restarts command block execution. in the rt mode, it enables the bcrtmp to receive a valid command. rt operation does not start until a valid command is received. when using this function: restart the bcrtmp after each master reset or programmed reset. this bit is not readable; verify operation by reading bit 0 of the bcrtmp?s status register.
bcrtmp-18 #1 status register (read only) these bits indicate the bcrtmp?s current status. bit number description bit 15 test. this bit reflects the inverse of the test output. it changes state simultaneously with the test output. bit 14 (rt) remote terminal active. indicates that the bcrtmp, in the remote terminal mode, is presently servicing a command. this bit reflects the inverse of the comstr pin. bit 13 (rt) dynamic bus control acceptance. this bit reflects the state of the dynamic bus control acceptance bit in the rt status word (see register 10 on page 20). bit 12 (rt) terminal flag bit is set in rt status word. see also section 8.2.8.10. bit 11 (rt) service request bit is set in rt status word. see also section 8.2.8.4. bit 10 (rt) busy bit is set in rt status word. see also section 8.2.8.7. bit 9 bit is in progress. bit 8 reset is in progress. this bit indicates that either a write to register 12 has just occurred or the bcrtmp has just received a reset remote terminal (#01000) mode code. this bit remains set less than 1ms. bit 7 bc/( rt ) mode. indicates the current mode of operation. a reset operation must be performed when changing between bc and rt modes. bit 6 channel a/ b . indicates either the channel presently in use or the last channel used. bit 5 subsystem fail indicator. indicates receiving a subsystem fail signal from the host subsystem on the ssysf input. bits 4-1 reserved. bit 0 (bc) command block execution is in progress. (rt) remote terminal is in operation. this bit reflects bit 0 of register 0. #2 current command block register (bc)/remote terminal descriptor space address register (rt) (bc) this register contains the address of the head pointer of the command block being executed. accessing a new command block updates it. (rt) the host cpu initializes this register to indicate the starting location of the rt descriptor space. the host must allocate 320 sequential locations following this starting address. for proper operation, this location must start on an i x 512 decimal address boundary, where i is an integer multiple. #3 polling compare register in the polling mode, the cpu sets the polling compare register to indicate the rt response word on which the bcrtmp should interrupt. this register is 11 bits wide, corresponding to bit times 9 through 19 of the rt?s 1553 status word response. the sync, remote terminal address, and parity bits are not included (see the section on polling, page 38). #4 bit (built-in-test) word register the bcrtmp uses the contents of this register when it responds to the transmit bit word mode code (#10011). in addition, the bcrtmp writes to the two most significant bits of the bit word register in response to either an initiate self-test mode code (rt mode) or a write to register 11 (bit start command) to indicate a bit failure. if the bit word needs to be modified, it can be read out, modified, then rewritten to this register. note that if the processor writes a ?1? to either bit 14 or 15 of this register, it effectively induces a bit failure. also note that during normal rt operation, bits 10 through 13 of this register indicate specific types of message errors, as shown below. bit number description bit 15 channel b failure. bit 14 channel a failure. bit 13 word count error. bit 12 parity error. bit 11 manchester error. bit 10 remote terminal time-out. bits 9-0 bit word. the least significant ten bits of the bit word are user programmable.
bcrtmp-19 #5 current command register (read only) in the rt, this register contains the command currently being processed. when not processing a command, the bcrtmp stores the last command/status word transmitted on the 1553 bus in this register. this register is updated only when bit 0 of register 0 is set. in the bc mode, this register contains the most current command sent out on the 1553 bus. #6 interrupt log list pointer register initialized by the cpu, the interrupt log list pointer register indicates the start of the interrupt log list. after each list e ntry, the bcrtmp updates this register with the address of the next entry in the list. (see page 46-47.) #7 high-priority interrupt enable register (read/write) setting the bits in this register causes a high-priority interrupt when the enabled event occurs. if enabled in register 14, set ting these bits also determines which events trigger the stop enable feature. to service the high-priority interrupt, the user reads register 8 to determine the cause of the interrupt, then writes to register 8 to clear the appropriate bits. the bcrtmp also provides a standard priority interrupt scheme that does not require host intervention. if high-priority interrupt service is not possible in a given application, it is advisable to use the standard priority features. bit number description bits 15-9 reserved. bit 8 data overrun enable. when set, this bit enables an interrupt when dmag was not received by the bcrtmp within the allotted time needed for a successful data transfer to memory. bit 7 (bc) illogical command error enable. this bit enables a high-priority interrupt to be asserted upon the occurrence of an illogical command. illogical commands include incorrectly formatted rt-rt command blocks. bit 6 (rt) dynamic bus control mode code interrupt enable. when set, an interrupt is asserted when the dynamic bus control mode code is received, provided the t/r bit is ?1,? the command is legal, and domc is active. bit 5 subsystem fail enable. when set, a high-priority interrupt is asserted after receiving a subsystem fail (ssysf) input pin. bit 4 end of bit enable. this bit indicates the end of the internal bit routine. bit 3 bit word fail enable. this bit enables an interrupt indicating that the bcrtmp detected a bit failure. bit 2 (bc) end of command block list enable (see command block control word, page 38.) this interrupt can be superseded by other high-priority interrupts. bit 1 message error enable. if enabled, a high-priority interrupt is asserted at the occurrence of a message error. if a high-priority interrupt condition occurs, as the result of an enabled message error, the device will halt operation until the user clears the interrupt by writing a ?1? to bit 1 of the high-priority interrupt status/reset register (reg. #8). if this interrupt is not cleared, the bcrtmp remains in the halted state (appearing to be ?locked up?), even if it receives a valid message. this high-priority interrupt scheme is necessary in order to maintain the bcrt mp?s state of operation so that the host cpu has this information available at the time of interrupt service. bit 0 standard interrupt enable. setting this bit enables the stdintl pin, but does not cause a high-priority interrupt. if the user wants the stop enable feature activated for standard interrupts, this bit must be set. if low, only the stdintl pin is asserted when a standard interrupt occurs.
bcrtmp-20 #8 high-priority interrupt status/reset register when a high-priority interrupt is asserted, this register indicates the event that caused it. to clear the interrupt signal and reset the bit, write a ?1? to the appropriate bit. see the corresponding bit definitions of register 7, high-priority interrupt enable register. bit number description bits 15-9 reserved. bit 8 data overrun. bit 7 illogical command. bit 6 dynamic bus control accepted. bit 5 subsystem fail. bit 4 end of bit. bit 3 bit word fail. bit 2 end of command block. bit 1 message error. bit 0 standard interrupt. the bcrtmp sets this bit when any standard interrupt occurs, providing bit 0 of register 7 is enabled. #9 standard interrupt enable register this register enables standard interrupt logging for any of the following enabled events (standard interrupt logging can also occur for events enabled in the bc command block or rt subaddress/mode code descriptor): bit number description bits 15-6 reserved. bit 5 (rt) illegal broadcast command. when set, this bit enables an interrupt indicating that an illegal broadcast command has been received. bit 4 (rt) illegal command. when set, this bit enables an interrupt indicating that an illegal command has been received. bit 3 (bc) polling comparison match. this enables an interrupt indicating that a polling event has occurred. the user must also set bit 12 in the bc command block control word for this interrupt to occur. bit 2 (bc) retry fail. this bit enables an interrupt indicating that all the programmed number of retries have failed. bit 1 (bc, rt) message error event. this bit enables a standard interrupt for message errors. bit 0 (bc) command block interrupt and continue. this bit enables an interrupt indicating that a command block, with the interrupt and continue function enabled, has been executed.
bcrtmp-21 #10 remote terminal address register this register sets the remote terminal address via software. the change lock-out enable feature, when set, prevents the remote terminal address or the bcrtmp mode selection from changing. note that md4 also controls the effect of bits 9-15 on status word generation. see section 8.2.8. bit number description bit 15 (rt) instrumentation. setting this bit sets the rt status word instrumentation bit. bit 14 (rt) busy. setting this bit sets the rt status word busy bit. it does not inhibit data transfers to the subsystem. bit 13 (rt) subsystem fail. setting this bit sets the rt status word subsystem flag bit. in the rt mode, the subsystem fail is also logged into the message status word. bit 12 (rt) dynamic bus control acceptance. setting this bit sets the rt status word dynamic bus control acceptance bit when the bcrtmp receives the dynamic bus control mode code from the currently active bus controller. host intervention is required for the bcrtmp to take over as the active bus controller. bit 11 (rt) terminal flag. setting this bit sets the rt status word terminal flag bit; the terminal flag bit in the rt status word is also internally set if the bit fails. bit 10 (rt) service request. setting this bit sets the rt status word service request bit. bit 9 (rt) busy mode enable. setting this bit sets the rt status word busy bit and inhibits all data transfers to the subsystem. (see forced busy mode, section 8.2.4.) bit 8 bc/ rt mode select. this bit?s state reflects the external pin bcrtsel. it does not necessarily reflect the state of the chip, since the bc/ rt mode select is software-programmable via bit 10 of register 0. this bit is read-only. bit 7 change lock-out. this bit?s state reflects the external pin lock. when set, this bit indicates that changes to the rt address or the bc/ rt mode select are not allowed using internal registers. this bit is read-only. bit 6 remote terminal address parity error. this bit indicates a remote terminal address parity error. it appears after the remote terminal address is latched if a parity error exists. bit 5 remote terminal address parity. this is an odd parity input bit used with the remote terminal address. it ensures accurate recognition of the remote terminal address. bits 4-0 remote terminal address (bit 0 is the lsb). this reflects the rta4-0 inputs at master reset. modify the remote terminal address by writing to these bits. #11 bit start register (write only) any write (i.e., data = don?t care) to this register?s address location initiates the internal bit routine, which lasts 100 m s. verify using the bit-in-progress bit in the status register. if the bcrtmp is online (bit 0 of register 1 is high), a programmed reset (write to register 12) must precede a write to this register to initiate the internal bit. the bcrtmp?s self-test performs an internal wrap-around test between its manchester encoder and its two manchester decoders. if the bcrtmp detects a failure on either the primary or the secondary channel, it flags this failure by setting bit 14 of regis ter 4 (bit word register) for channel a and/or bit 15 for channel b. when in the remote terminal mode, while the bcrtmp is performing its self-test, it ignores any commands on the 1553 bus until it has completed the self-test. #12 programmed reset register (write only) any write (i.e., data = don?t care) to this register?s address location initiates a reset sequence of the encoder/decoder and pr otocol sections of the bcrtmp which lasts less than 1 m s. this is identical to the reset used for the reset remote terminal mode code except that command processing halts. for a total reset (i.e., including registers), see the mrst signal description. #13 rt timer reset register (write only) any write (i.e., data = don?t care) to this register?s address location resets the rt time tag timer to zero. the bcrtmp?s remot e terminal timer time-tags message transactions. the time tag is generated from a free-running eight-bit timer of 64 m s resolution. this timer can be reset to zero simply by writing to register 13. when the timer is reset, it immediately starts running.
bcrtmp-22 #14 activity status/operational mode register bit number description bits 15-14 reserved. bit 13 ignore t/r bit in mode command. when high, this bit causes the bcrtmp to ignore the value of the t/r bit in 1553 mode commands 0-15 (mode codes without data) and prevents automatic execution of modes 18-19. this feature is used in conjunction with operational mode 6 (input pin md6). bit 12 stop enable. when the bcrtmp is in the rt mode, this bit enables a feature that places the bcrtmp into the forced busy mode when an interrupt (either standard or high-priority) occurs. when the bcrtmp enters the forced busy mode, the device responds with the busy bit set in the 1553 status word any time a valid 1553 command is received. when the interrupt is cleared, the bcrtmp exits the forced busy mode. for bc operation, setting the stop enable bit causes the bcrtmp to halt command block execution when an enabled interrupt (either standard or high-priority) occurs. command block execution resumes when the user clears the interrupt by writing a ?1? to the appropriate bit in register 8. bit 11 bus b active. this bit goes high when the bcrtmp, acting as a remote terminal, receives a valid 1553 command on the secondary bus. bit 10 bus a active. this bit goes high when the bcrtmp, acting as a remote terminal, receives a valid 1553 command on the primary bus. bit 9 wrapf wrap-around test fail. this bit reflects the state of the wrapf output signal. bit 8 altwrap alternate channel wrap-around test enable. after master reset, this bit reflects the complement of the state of the altwrap input signal. this bit can be software-modified if the lock pin is low. thus, to enable the altwrap feature, write a one to this bit location. bit 7 wrapen wrap-around test enable. after master reset, this bit reflects the complement of the state of the wrapen input signal. this bit can be software-modified if the lock pin is low. thus, to enable the wrapen feature, write a one to this bit location. bit 6 md6 operational mode 6. after master reset, this bit reflects the state of the corresponding input pin (md6). see section 8.1.7 for a summary of operational mode 6. this bit can be software-modified if the lock pin is low. bit 5 md5 operational mode 5. after master reset, this bit reflects the state of the corresponding input pin (md5). see section 8.1.6 for a summary of operational mode 5. this bit can be software-modified if the lock pin is low. bit 4 md4 operational mode 4. after master reset, this bit reflects the state of the corresponding input pin (md4). see section 8.1.5 for a summary of operational mode 4. this bit can be software-modified if the lock pin is low. bit 3 md3 operational mode 3. after master reset, this bit reflects the state of the corresponding input pin (md3). see section 8.1.4 for a summary of operational mode 3. this bit can be software-modified if the lock pin is low. bit 2 md2 operational mode 2. after master reset, this bit reflects the state of the corresponding input pin (md2). see section 8.1.3 for a summary of operational mode 2. this bit can be software-modified if the lock pin is low. bit 1 md1 operational mode 1. after master reset, this bit reflects the state of the corresponding input pin (md1). see section 8.1.2 for a summary of operational mode . this bit can be software-modified if the lock pin is low. bit 0 md0 operational mode 0. after master reset, this bit reflects the state of the corresponding input pin (md0). see section 8.1.1 for a summary of operational mode 0. this bit can be software-modified if the lock pin is low.
bcrtmp-23 #15 programmable status/last status word register (rt) this register provides control of and access to the rt status word. bits 15-12 (read/write) allow for special operations on some or all of the status word bits. writing to bit 11 places the bcrtmp into the forced busy mode. reading this bit will verify that the bcrtmp has entered the forced busy mode (see section 8.2.4). writing to the remaining bits (bits 10-0) of this register allo ws control of the rt status word (see section 8.2.8). when reading from this register, bits 10-0 indicate the last status word sent by the bcrtmp. bit number description bit 15 immediate clear mode enable. when set, this bit will cause the bcrtmp to automatically clear all programmable status bits (bits 10-0 of this register and bits 15-9 of register 10) after the bcrtmp transmits the rt status word. when this bit is set, the first status word sent out contains the status word created from the programmable status bits in this register, register 10, and from internally generated conditions (see section 8.2.8). after status word transmission, the bcrtmp clears bits 10-0 of this register and bits 15-9 of register 10. there is one exception to this automatic status bit clearing. when the next command received is the transmit status word or transmit last command mode code, the bcrtmp will respond with the appropriate status word from the previous valid command. this feature applies to all operational modes. note that inhibition of the terminal flag bit (receipt of mode code 6) is also cleared by this bit. bit 14 automatic terminal flag bit enable, option 1. when set, this bit will cause the terminal flag to be automatically set when any of the status word field bits are set (status word bit times 9 through 18). bit 13 automatic terminal flag bit enable, option 2. when set, this bit will cause the terminal flag to be automatically set when the busy or subsystem flag status word bits are set. if both bits 14 and 13 of this register are set, neither option is selected, and the busy bit will not be set by the forced busy mode. these automatic terminal flag bit options apply for all operational modes. bit 12 automatic data ready. this bit, when set, causes the bcrtmp to place the complement of the busy bit in the data ready bit (bit 8). therefore, when the bcrtmp transmits the status word, bit 8 = not bit 3. bit 11 forced busy. bit 10 me message error (bit time 9)/last status word message error bit. bit 9 psbt10 programmable status bit time 10/last status word bit time 10. bit 8 psbt11 programmable status bit time 11/last status word bit time 11. bit 7 psbt12 programmable status bit time 12/last status word bit time 12. bit 6 psbt13 programmable status bit time 13/last status word bit time 13. bit 5 psbt14 programmable status bit time 14/last status word bit time 14. bit 4 psbt15 programmable status bit time 15/last status word bit time 15. bit 3 psbt16 programmable status bit time 16/last status word bit time 16. bit 2 psbt17 programmable status bit time 17/last status word bit time 17. bit 1 psbt18 programmable status bit time 18/last status word bit time 18. bit 0 tf terminal flag (bit time 19)/last status word terminal flag bit.
bcrtmp-24 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 #0 rtyto unused unused unused unused rto unused unused unused a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 (bc) current command block register test rtact dynbus rt flag srq busy bit reset bc/rt busa/b ssfail cmbkpg bc/rt status register extovr bc/rt rtyaltb busben busaen chnsel rtycnt rtybcme rtyme rtybsy sten bc/rt control register #3 #2 #1 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 (rt) remote terminal descriptor space address register polling compare register tf swbt18 swbt17 swbt16 swbt15 swbt14 swbt13 swbt12 swbt11 swbt10 msgerr x x x x x d7 d6 d5 d4 d3 d2 d1 d0 current command register rtto d9 d8 #4 #5 bit word register chbfail chafail wcerr parerr manerr 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 d7 d6 d5 d4 d3 d2 d1 d0 d10 d9 d8 d15 d14 d13 d12 d11 unused unused unused unused unused unused #7 #6 interrupt log list pointer register a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 bcrtmp high-priorityinterrupt enable register stdint msgerr eol bitfail endbit ssfail dynbus illcmd datovr unused 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 table 1. bcrtmp registers
bcrtmp-25 #12 #13 programmed reset register remote terminal timer reset register x x x x x x x x x x x x x x x x 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 x x x x x x x x x x x x x x x x 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 15 14 13 12 11 10 9 8 0 1 2 3 4 5 6 7 x instr busy1 busy2 ss flag dbc rt flag srq bc/rt lock parerr rtapar rta4 rta3 rta2 rta1 rta0 illbcmd illcmd polmtch rtyfail msgerr cmdblk built-in-test start register remote terminal address register standard interrupt enable register #11 #10 #9 15 14 13 12 11 10 9 8 unused unused unused unused unused unused unused unused 0 1 2 3 4 5 6 7 unused unused 15 14 13 12 11 10 9 8 0 1 2 3 4 5 6 7 x x x x x x x x x x x x x x x #14 activity status/operational mode register md0 md1 md2 md3 md4 md5 md6 wrpen altwrap wrapf a act b act stpen ignortr unused unused 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 #15 programmable status register tf psbt18 psbt12 psbt11 psbt10 me fbusy ps8=nb tf opt2 tf opt1 imm clr 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 datovr illcmd bcrtmp high-priorityinterrupt status/reset register #8 15 14 13 12 11 10 9 8 unused unused unused unused unused unused unused 0 1 2 3 4 5 6 7 dynbus ssfail endbit bitfail eol msgerr stdint psbt13 psbt14 psbt15 psbt16 psbt17 x = don?t care table 1. bcrtmp registers (continued from page 24)
bcrtmp-26 4.0 s y s t e m o v e r v i e w the bcrtmp can be configured for a variety of processor and memory environments. the host processor and the bcrtmp communicate via a flexible, programmable interrupt structure, internal registers, and a user-definable shared memory area. the shared memory area (up to 64k) is completely user-programmable and communicates bcrtmp control information -- message data, and status/ error information. built-in memory management functions designed specifically for mil-std-1553 applications aid processor off-loading. the host needs only to establish the parameters within memory so the bcrtmp can access this information as required. for example, in the rt mode, the bcrtmp can store data associated with individual subaddresses anywhere within its 64k address space. the bcrtmp then can automatically buffer up to 128 incoming messages of the same subaddress, thus preventing the previous messages from being overwritten by subsequent messages. this buffering also extends the intervals required by the host processor to service the data. selecting an appropriate mclk frequency to meet system memory access time requirements controls the memory access rate. the completion of a user-defined task or the occurrence of a user-selected event is indicated by using the extensive set of interrupts provided. in the bc mode, the bcrtmp can process multiple messages, assist in scheduling message lists, and provide host-programmable functions such as auto retry. the bcrtmp is incorporated in systems with a variety of interrupt latencies by using the interrupt history list feature (see exception handling and interrupt logging, page 46). the interrupt history list sequentially stores the events that caused the interrupt in memory without losing information if a host processor does not respond immediately to an interrupt. 5.0 s y s t e m i n t e r f a c e 5.1 dma transfers the bcrtmp initiates dma transfers whenever it executes command blocks (bc mode) or services commands (rt mode). dmar initiates the transfer and is terminated by the inactive edge of dmack . the address enable (aen) input enables the bcrtmp to output an address onto the address bus. the bcrtmp requests transfer cycles by asserting the dmar output, and initiates them when a dmag input is received. a dmack output indicates that the bcrtmp has control of the data and address buses. the tsctl output is asserted when the bcrtmp is actually asserting the address and data buses. to support using multiple bus masters in a system, the bcrtmp outputs the dmago signal that results from the dmag signal passing through the chip when a bcrtmp bus request was not generated ( dmar inactive). you can use dmago in daisy-chained multimaster systems. 5.2 hardware interface the bcrtmp provides a simple subsystem interface and facilitates dma arbitration. the user can configure the bcrtmp to operate in a variety of memory-processor environments including pseudo-dual-port ram and standard dma configurations. for complete circuit description, such as arbitration logic and i/o, please refer to the appropriate application note. 5.3 cpu interconnection pseudo-dual-port ram configuration the bcrtmp?s address and data buses connect directly to ram, with buffers isolating the bcrtmp?s buses from those of the host cpu (figures 3a and 3b). the cpu?s memory control signals ( rd , wr , and memcsi ) pass through the bcrtmp and connect to memory as rrd , rwr , and memcso . standard dma configuration the bcrtmp?s and cpu?s data, address, and control signals are connected to each other as shown in figures 3c and 3d. the rwr , rrd , and memcso are activated after dmag is asserted. ram bcrtmp cpu memory control signals rrd rwr memcso rd memcsi wr figure 3a. pseudo-dual-port ram control signals
bcrtmp-27 in either case, the bcrtmp?s address and data buses remain in a high-impedance state unless the cs and rd signals are active, indicating a host register access; or tsctl is asserted, indicating a memory access by the bcrtmp. cpu attempts to access bcrtmp registers are ignored during bcrtmp memory access. inhibit dma transfers by using the busy function in the remote terminal address register while operating in the remote terminal mode. the designer can use tsctl to indicate when the bcrtmp is accessing memory. aen is also available (use is optional), giving the cpu control over the bcrtmp?s address bus. a dma burst (burst) signal indicates multiple dma accesses. bcrtmp cpu shared memory area address bus data bus figure 3c. dma signals oe we cs dma dma dmac rrd rwr memcso 1553 bus bus b bus a xfmr xfmr (dual redundant) bcrtmp control/arbitration control cpu host buffers 16 address 16 data ram dual transceiver transmitter timeout figure 3b. cpu/bcrtmp interface -- pseudo-dual-port ram configuration
bcrtmp-28 register access registers 0 through 15 are accessed with the decode of the four lsbs of the address bus (a0-a3) and asserting cs . pulse either rd or wr for multiple register accesses. 5.4 ram interface the bcrtmp?s rrd , rwr , and memcso signals serve as read and write controls during bcrtmp memory accesses. the host subsystem signals rd , wr , and memcsi propagate through the bcrtmp to become rrd , rwr , and memcso outputs to support a pseudo-dual- port. during bcrtmp-ram data transfers, the host subsystem?s memory signals are ignored until the bcrtmp access is complete. 5.5 legalization bus in the rt mode, when the ut1553 bcrtmp receives a command on the 1553 bus, it must determine whether that command is legal. the bcrtmp provides two methods for the designer to accomplish this task. with the first method, called dma legalization, the bcrtmp automatically accesses a specific descriptor block when it receives a command to a given subaddress (or mode code). this descriptor block (see figure 4a) contains information that the bcrtmp uses to determine if the command is legal or illegal. with the second method, called bus legalization, the 1553 command word, minus the rt address, is routed to the legalization bus outputs of the bcrtmp (see figure 4b). the bcrtmp uses this information, for example, as a prom address. the single-bit output from the prom then feeds the lglcmd input signal of the bcrtmp (see figure 4c). if the command is legal, the prom output is high; if the command is illegal, the prom output is low. figure 31 shows the required timing for the bcrtmp legalization bus. 1553 bus bus b bus a xfmr xfmr dual transceiver memory arbitration control address data bcrtmp cpu ram buffer figure 3d. cpu/bcrtmp interface -- dma configuration
bcrtmp-29 the descriptor pointer register (register 2) combined with the command word generates the address of the control word for the descriptor block fetch. the control word contains legalization information. figure 4a. bcrtmp descriptor block legalization ram control word message status pointer data list pointer unused control word message status pointer data list pointer unused control word message status pointer data list pointer unused descriptor block last mode code descriptor block descriptor block first receive subaddress second receive subaddress bcrtmp dma fetch of three words when command is received. 2 sync 1 command 3 combinational logic figure 4b. bcrtmp legalization bus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1553 command word bit time 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 rt address subaddress/ mode word count or mode code t/r lgl0 lgl1 lgl2 lgl3 lgl4 lgl5 lgl6 lgl7 lgl8 lgl9 lgl10 mc brdcast combinational logic
bcrtmp-30 to facilitate on-board programming of the 5-volt eeproms on the host board, the bcrtmp places the legalization bus into the high-impedance state when the user asserts the mrst signal. 5.6 transmitter/receiver interface the bcrtmp?s manchester ii encoder/decoder interfaces directly with the 1553 bus transceiver, using the tao-taz and raz-rao signals for channel a, and tbo-tbz and rbz-rbo signals for channel b. the bcrtmp also provides timrona and timronb signal outputs and an active channel output indicator (cha/ b ) to assist in meeting the mil-std-1553b fail-safe timer requirements (see figure 5). address decoder figure 4c. bcrtmp bus legalization example fifo bcrtmp legalization prom data out shift out shift in data in err lgl0 - lgl4 legalization bus lglen lglcmd microprocessor ram address bus data bus optional for a3818 message error logging 5 5 bcrtmp channel a channel b dual txinha txinhb channel a channel b transceiver timrona timronb cha/ b figure 5. dual-channel transceiver
bcrtmp-31 6.0 r e m o t e t e r m i n a l a r c h i t e c t u r e the remote terminal architecture is a descriptor- based configuration of relevant parameters. it is composed of an rt descriptor space (see figure 6) and internal, host- programmable registers. the descriptor space contains only descriptors. descriptors contain programmable subaddress parameters relating to handling message transfers. each descriptor consists of four words: (1) a control word, (2) a message status list pointer, (3) a data list pointer, and (4) an unused fourth word (see figure 7.) these words indicate how to perform the data transfers associated with the designated subaddress. a receive descriptor and a transmit descriptor are associated with each subaddress. the descriptors reside in memory and are listed sequentially by subaddress. by using the index within the descriptor, the bcrtmp can buffer incoming and outgoing messages, which reduces host cpu overhead. this message buffering also reduces the risk of incoming messages being overwritten by subsequent incoming messages. each descriptor contains a programmable interrupt structure for subsystem notification of user-selected message transfers and indicates when the message buffers are full. illegalizing subaddresses, in normal and broadcast modes, is accomplished by using programmable bits within the descriptor (see the rt functional operation section below). message status information -- including word count, an internally generated time tag, and broadcast and message validity information -- is provided for each message. the message status words are stored in a separate message status word list according to subaddress. the list?s starting locations are programmable within the descriptor. message data, received or transmitted, is also stored in lists. the message capacity of the lists and the lists? locations are user selectable within the descriptor. 6.1 rt functional operation the rt off-loads the host computer of all routine data transfers involved with message transfers over the 1553 bus by providing a wide range of user-programmable functions. these functions make the bcrtmp?s operation flexible for a variety of applications. the following paragraphs give each function?s operational descriptions. 6.1.1 rt subaddress descriptor definition the host sets words within the descriptor. the bcrtmp then reads the descriptor words when servicing a command corresponding to the specified descriptor. all bit-selectable functions are active high and inhibited when low. #?s 15 & 31 #?s 1 & 17 #?s 0 & 16 - starting address initialized by cpu in the rt descriptor transmit subaddress subaddress subaddress subaddress subaddress #1 #2 #31 #1 #2 #31 subaddress mode code mode code mode code receive receive receive unused transmit transmit unused space register figure 6. descriptor space for future expansion data list pointer message status list pointer index 0 6 8 15 unused i i 10 i i 9 7 illegal broadcast subaddress illegal interrupt when addressed interrupt when index = 0 subaddress figure 7. remote terminal subaddress descriptor
bcrtmp-32 a. control word. the first word in the descriptor, the control word, selects or disables message transfers and selects an index. bit number description bits 15-11 reserved. bit 10 illegal broadcast subaddress. indicates to the bcrtmp not to access this subaddress using broadcast commands. the message error bit in the status word is set if the illegal broadcast subaddress is addressed. since transmit commands do not apply to broadcast, this bit applies only to receive commands. bit 9 illegal subaddress. set by the host cpu, it indicates to the bcrtmp that a command with this subaddress is illegal. if a command uses an illegal subaddress the message error bit in the 1553 status word is set. the illegal command interrupt is also asserted if enabled. bit 8 interrupt upon valid command received. indicates that the bcrtmp is to assert an interrupt every time a command addresses this descriptor. the interrupt occurs just prior to post-command descriptor updating. bit 7 interrupt when index = 0. indicates that the bcrtmp initiates an interrupt when the index is decremented to zero. bits 6-0 index. these bits are for indexed message buffering. indexing means transacting a pre-specified number of messages before notifying the host cpu. after each message transaction, the bcrtmp decrements the index by one until index = 0. note that the index is decremented for messages that contain message errors. b. message status list pointer. the host sets the message status list pointer, the second word within the descriptor, and the bcrtmp uses it as a starting address for the message status list. it is incremented by one with each message status word write. if the control word index is already equal to zero, the message status list pointer is not incremented and the previous message status word is overwritten. note: a message status word is written and the pointer is incremented when the bcrtmp detects a message error. c. data list pointer. the data list pointer is the third word within the descriptor. the bcrtmp stores data in ram beginning at the address indicated by the data list pointer. the data list pointer is updated at the end of each successful message with the next message?s starting address with the following exceptions: if the message is erroneous, the data list pointer is not updated. the next message overwrites any data corresponding to the erroneous message. upon receiving a message, if the index is already equal to zero, the data list pointer is not incremented and data from the previous message is overwritten. d. reserved. the fourth descriptor word is reserved for future use.
bcrtmp-33 6.1.2 message status word each message the bcrtmp transacts has a corresponding message status word, which is pointed to by the message status list pointer of the descriptor. this word allows the host cpu to evaluate the message?s validity, determine the word count, and calculate the approximate time frame in which the message was transacted (figures 8 and 9). message status word definition bit number description bit 15 subsystem failed. indicates ssysf was asserted before the message status word transfer to memory. this bit is also set when the user sets bit 13 of register 10. bit 14 broadcast message. indicates that the corresponding message was received in the broadcast mode. bit 13 message error. indicates a message is invalid due to improper synchronization, bit count, word count, or manchester error. bits 12-8 word count. indicates the number of words in the message and reflects the word count field in the command word. should the message contain a different number of words than the word count field, the message error flag is triggered. if there are too many words, they are withheld from ram. if the actual word count is less than it should be, the message error bit in the 1553 status word is set. bits 7-0 time tag. the bcrtmp writes the internally generated time tag to this location after message completion. the resolution is 64 m s. (see register 13). if the timer reads 2, it indicates the message was completed 128 to 191 m s after the timer started. asserted during this message message error message was broadcasted subsystem fail input was figure 8. message status word word count time tag 15 14 13 12 8 7 0 message message message message message (from rt descriptor) figure 9. remote terminal data and message status list #5 #4 #3 #2 #1 #5 #4 #3 #2 #1 list message status word data list pointer data list list pointer message status
bcrtmp-34 6.1.3 mode code descriptor definition mode codes are handled similarly to subaddress transactions. both use the four-word descriptors residing in the rt descriptor space to allow the host to program their operational mode. corresponding to each mode code is a descriptor (see figure 10a). of the 32 address combinations for mode codes in mil-std-1553, some are clearly defined functions while others are reserved for future use. sixteen descriptors are used for mode code operations with each descriptor handling two mode codes: one mode code with an associated data word and one mode code without an associated data word. all mode codes can be handled in accordance with mil-std-1553b. the function of the first word of the mode code descriptor is similar to that of the subaddress descriptor and is defined below. the remaining three words serve the same purpose as in the subaddress descriptor. control word bit number description bit 15 interrupt on reception of mode code (without data word). bit 14 illegalize broadcast mode code (without data word). bit 13 illegalize mode code (without data word). bit 12 reserved. bit 11 illegalize broadcast mode code (with data word). bit 10 illegalize transmit mode code (with data word). bit 9 illegalize receive mode code (with data word). bit 8 interrupt on reception of mode code (with data word). bit 7 interrupt if index = 0. bits 6-0 index. functionally equivalent to the index described in the subaddress descriptor. it applies to mode codes with data words only. figure 10a. (rt) mode codedescriptor space rtdssa + 320 mode code mode code mode code (rtdssa) + 256 starting address descriptor space remote terminal #?s 15 & 31 #?s 2 & 18 #?s 1 & 17 #?s 0 & 16 mode code note: mode code descriptor blocks are also provided for reserved mode codes but have no associated predefined bcrtmp operation. 15 14 13 12 11 10 9 8 7 6 0 message status list pointer data list pointer reserved index illegalize broadcast modecode (without data word) interrupt on reception of mode code (without data word) illegalize mode code (without data word) reserved illegalize broadcast modecode (with data word) illegalize receive mode code (with data word) interrupt on reception of mode code (with data word) interrupt if index = 0 illegalize transmit mode code (with data word) figure 10b. (rt) mode codedescriptor
bcrtmp-35 the descriptors, numbered sequentially from 0 to 15, correspond to mode codes 0 to 15 without data words and mode codes 16 to 31 with data words. for example, mode codes 0 and 16 correspond to descriptor 0 and mode codes 1 and 17 correspond to descriptor 1. the mode code descriptor space is appended to the subaddress descriptor space starting at 0100h (256d) of the 320-word rt descriptor space (see figure 6). the bcrtmp can autonomously support all mode codes without data words by executing the specific function and transmitting the 1553 status word. the subsystem provides the data word for mode codes with data words (see the data list pointer section). for all mode codes, an interrupt can be asserted by setting the appropriate bit in the control word upon successful completion of the mode command (see figure 10b). dynamic bus control #00000 this mode code is accepted automatically if the dynamic bus control enable bit in the remote terminal address register is set. setting the dynamic bus control acceptance bit in the 1553 status word and bcrtmp status register confirms the mode code acceptance. a high- priority interrupt is also asserted if enabled. if the dynamic bus control enable bit is not set, the bcrtmp does not accept dynamic bus control. synchronize (without data word) #00001 if enabled in the mode code #00001 descriptor control word, the bcrtmp asserts an interrupt when this mode code is received. transmit status word #00010 the bcrtmp automatically transmits the 1553 status word corresponding to the last message transacted. initiate self-test #00011 the bcrtmp automatically starts its bit routine. an interrupt, if enabled, is asserted when the test is completed. the bit word register and external pin bcrtf are updated when the test is completed. a failure in bit will also set the tf status word bit. transmitter shutdown #00100 the bcrtmp disables the channel opposite the channel on which the command was received. override transmitter shutdown #00101 the bcrtmp enables the channel previously disabled. inhibit terminal flag bit #00110 the bcrtmp inhibits the terminal flag from being set in the status word. override inhibit terminal flag bit #00111 the bcrtmp disables the terminal flag inhibit. reset remote terminal #01000 the bcrtmp automatically resets the encoder, decoders, and protocol logic. transmit vector word #10000 the bcrtmp transmits the vector word from the location addressed by the data list pointer in the mode code descriptor block. synchronize (with data word) #10001 on receiving this mode code, the bcrtmp simply stores the associated data word. transmit last command #10010 the bcrtmp transmits the last command executed and the corresponding 1553 status word. transmit bit word #10011 the bcrtmp transmits bit information from the bit register. selected transmitter shutdown #10100 on receiving this mode code, the bcrtmp simply stores the associated data word. override selected transmitter shutdown #10101 on receiving this mode code, the bcrtmp simply stores the associated data word. mode codes 9-15 and 22-31 are reserved for future expansion of mil-std-1553. 6.2 rt error detection in accordance with mil-std-1553, the remote terminal handles superseding commands on the same or opposite bus. when receiving, the remote terminal performs a response time-out function of 56ms for rt-rt transfers. if the response time-out condition occurs, a message error bit can be set in the 1553 status word and in the message status word. error checking occurs on both of the manchester logic and the word formats. detectable errors include word count errors, long words, short words, manchester errors (including zero crossing deviation), parity errors, and data discontiguity. 6.3 rt operational sequence the following is a general description of the typical behavior of the bcrtmp as it processes a message in the rt mode. it is assumed that the user has already written a ?1? to register 0, bit 0, enabling rt operation.
bcrtmp-36 valid command received. comstr goes active bus legalization occurs (if selected) dma descriptor read. (if bus legalization is used, the bcrtmp ignores the legalization information in the control word). after receiving a valid command, the bcrtmp initiates a burst dma: dma arbitration (burst) control word read message status list pointer read data list pointer read data transmitted/received. data word dma. if the bcrtmp needs to transmit data from memory, it initiates a dma cycle for each data word shortly before the data word is needed on the 1553b bus: dma arbitration data word read (starting at data list pointer address, incremented for each successive word) if the bcrtmp receives data, it writes each data word to memory after the data word is received: dma arbitration data word write (starting at data list pointer address, incremented for each successive word) status word transmission. the bcrtmp automatically transmits the status word as described in section 8.2.8. for illegalized commands, the bcrtmp also sets the message error bit in the 1553 status word. exception handling. if an interrupting condition occurs during the message, the following occurs: for high-priority interrupts: hpint is asserted (if enabled in register 7). for message errors, the bcrtmp is put in a hold state until the interrupt is acknowledged (by writing a ?1? to the appropriate bit in register 8). for standard interrupts: dma arbitration (burst) interrupt status word write rt descriptor block pointer write tail pointer read (into register 6) stdintp pulses low stdintl asserted (if enabled) processing continues descriptor write. after the bcrtmp processes the message, a final dma burst occurs to update the descriptor block, if necessary: dma arbitration (burst) message status word write data list pointer write (incremented by word count) message status list pointer write (incremented by 1) control word write (index decremented) note the following exceptions: mode codes without data require no descriptor update. illegalized commands require no description updates (or data word accesses). predefined mode codes (18 and 19) which do not require access to memory for the data word, do not involve updating the data list pointer. messages with errors prevent updates to the data list pointer. if the message index was zero, neither the message status list pointer nor the data list pointer is updated. 7.0 b u s c o n t r o l l e r a r c h i t e c t u r e the bcrtmp?s bus controller architecture is based on a command block structure and internal, host- programmable registers. each message transacted over the mil-std-1553 bus has an associated command block, which the cpu sets up (see figures 11 and 12). the command block contains all the relevant message and rt status information as well as programmable function bits that allow the user to select functions and interrupts. this memory interface system is flexible due to a doubly-linked list data structure figure 11. command block head pointer control word command word 1 command word 2 (rt-rt only) data list pointer status word 1 status word 2 (rt-rt only) tail pointer
bcrtmp-37 in a doubly-linked command block structure, pointers delimit each command block to the previous and successive blocks (see figure 13). the linking feature eases multiple message processing tasks and supports message scheduling because of its ability to loop through a series of transfers at a predetermined cycle time. a data pointer in the command allows efficient space allocation because data blocks only have to be configured to the exact word count used in the message. data pointers also provide flexibility in data-bank switching. a control word with bit-programmable functions and a message error bit are in each command block. this allows selecting individual functions for each message and provides message validity information. the bcrtmp?s register set provides additional global parameters and address pointers. a programmable auto retry function is selectable from the control word and control register. the auto retry can be activated when any of the following occurs: busy bit set in the status word message error (indicated by the rt status response) response time-out message error detected by the bus controller one to four retries are programmable on the same or opposite bus. the bus controller also has a programmable intermessage delay timer that facilitates message transfer scheduling (see figures 14 and 15). this timer, programmed in the control word, automatically delays between the start of two successive commands. a polling function is also provided. the bus controller, when programmed, compares incoming status words to a host-specified status word and generates an interrupt if the comparison indicates any matching bits. an interrupt and continue function facilitates the host subsystem?s synchronization by generating an interrupt when the specified command block?s message is executed. 7.1 bc functional operation the bus controller off-loads the host computer of many functions needed to coordinate 1553 bus data transfers. special architectural features provide message- by-message flexibility. in addition, a programmable interrupt scheme, programmable intermessage timing delays, and internal registers enhance the bcrtmp?s operation. the host determines the first command block by setting the initial starting address in the current command block register. once set, the bcrtmp updates the current command block register with the next command block address. the bcrtmp then executes the sequential command blocks and counts out message delays (where programmed) until it encounters the last command block listed (indicated by the end of list bit in the control word). interrupts are asserted when enabled events occur (see section 9.0, exception handling and interrupt logging). the functions and their programming instructions are described below. the registers also contain many programmable functions and function parameters. x x is between 1 & 32 last data word data word #2 data word #1 data list pointer command block figure 12. data placement command block #1 hp tp #2 hp tp #3 hp tp #4 hp tp figure 13. command block chaining
bcrtmp-38 bc command block definition each command block contains (see figure 11): a. head pointer. host-written, this location can contain the address of the previous command block?s head pointer. the bcrtmp does not access this location. b. control word. host-written, the control word contains bit-selectable options and a message error bit the bcrtmp provides (see figure 14). the bit definitions follow. bit number description bit 15 message error. the bcrtmp sets this bit when it detects an invalid rt response as defined in mil-std 1553b. bit 14 skip. when set, this bit instructs the bcrtmp to skip this command block and execute the next. bit 13 interrupt and continue. if set, a standard interrupt is asserted when this block is addressed; operation, however, continues. note that this interrupt must also be enabled by setting bit 0 of register 9. bit 12 polling enable. enables the bcrtmp?s polling operation. bit 11 auto retry enable. when set, the auto retry function, governed by the global parameters in the control register, is enabled for this message. bit 10 end of list. set by the cpu, this bit indicates that the bcrtmp, upon completion of the current message, will halt (register 1, bit 0 goes inactive) and assert a high-priority interrupt. the interrupt must also be enabled in thehigh-priority interrupt enable register. bit 9 rt-rt. set by the cpu, this indicates that this command block transacts an rt-rt transfer. bit 8 monitor rt-rt transfer. set by the cpu, this function indicates that the bcrtmp should receive and store the message beginning at the location indicated by the data pointer. bits 7-0 time delay. the cpu sets this field, which causes the bcrtmp to delay the specified time between sequential message starts (see figures 14 and 15). regardless of the value in the time delay field (including zero), the bcrtmp will at least meet the minimum 4 m s intermessage gap time as specified in mil-std-1553b. the timer is enabled by having a non-zero value in this bit field. when using this function, please note: timer resolution is 16 m s. as an example, if a given message requires 116 m s to complete (including the minimum 4ms intermessage gap time) the value in the time delay field must be at least 00001000 (8 x 16 m s = 128 m s) to provide an intermessage gap greater than the 4ms minimum requirement. if the timer is enabled and the skip bit is set, the timer provides the programmed delay before proceeding. if the message duration exceeds the timer delay, the message is completed just as if the time were not enabled. ?time delay? transfer rt-rt monitor transfer rt-rt list of end enable retry auto enable polling continue and interrupt error message skip 15 14 13 12 11 10 9 8 7 0 figure 14. command word figure 15. bc timing delays message #1 message #2 message #3 t delay1 t delay2
bcrtmp-39 c. command word one. initialized by the cpu, this location contains the first command word corresponding to the command block?s message transfer. d. command word two. initialized by the cpu, this location is for the second (transmit) command word in rt-rt transfers. in messages involving only one rt, the location is unused. e. data pointer. initialized by the cpu, this location contains the starting location in ram for the command block?s message (see figure 16). f. status word one. stored by the bcrtmp, this location contains the entire remote terminal status response. g. status word two. stored by the bcrtmp, this location contains the receiving remote terminal status word. for transfers involving one remote terminal, the location is unused. h. tail pointer. initialized by the host cpu, the tail pointer contains the next command block?s starting address. 7.2 polling during a typical polling scenario (see figure 17) the bus controller interrogates remote terminals by requesting them to transmit their status words. this feature can also alert the host if a bit is set in any rt status word response during normal message transactions. the bcrtmp enables the host to initialize a chain of command blocks with the command word?s polling enable bit. a programmable polling compare register (pcr) is provided. in the polling mode, the remote terminal response is compared to the polling compare register contents. program the pcr by setting the pcr bits corresponding to the rt?s 1553 status word bits to be compared. if they match (i.e., two 1?s in the same bit position) then, if enabled in both the bc command block control word and in the standard interrupt enable register (register 9), a polling comparison interrupt is generated. example 1. no bit match is present pcr 0000000001 rt?s 1553 status word response 0000010000 result no polling comparison interrupt example 2. bit match is present pcr 0010010000 rt?s 1553 status word response 00000100000 result polling comparison interrupt 7.3 bc error detection the bus controller checks for errors on each message transaction. in addition, the bc compares the rt command word addresses to the incoming status word addresses. the bc monitors for response time-out and checks data and control words for proper format according to mil-std- 1553. illogical commands include incorrectly formatted rt-rt command blocks. figure 16. contiguous data storage command block #1 data pointer command block #2 data pointer message #1 message #2 ram data word #1 data word #2 data word #3 data word #1 data word #2 data word #3 data word #4 rt bc response q? rt rt polling response register (rt status word) polling compare word (set by cpu) figure 17. polling operation
bcrtmp-40 7.4 bus controller operational sequence the following is a general description of the typical behavior of the bcrtmp as it processes a message in the bc mode. the user starts bc operation by writing a ?1? to register 0, bit 0. command block dma - the following occurs immediately after bus controller startup: dma arbitration (burst) control word read command word 1 read (from third location of command block) data list pointer read a. for bc-to-rt command blocks: the bcrtmp transmits the command word. data word dma dma arbitration data word read (starting at data list pointer address, incremented for each successive word) the bcrtmp transmits the data word. data word dmas and transmissions continue until all data words are transmitted. status word dma the bcrtmp receives the rt status word. dma arbitration status word write (to sixth location of command block) b. for rt-to-bc command blocks: the bcrtmp transmits the command word. status word dma the bcrtmp receives the rt status word. dma arbitration status word write (to sixth location of command block) the bcrtmp receives the first data word. data word dma dma arbitration data word write (starting at data list pointer address, incremented for each successive word) data word receptions and dmas continue until all data words are received. c. for rt(a)-to-rt(b) command blocks: the bcrtmp transmits command word 1 to rt(b). command word 2 dma dma arbitration command word 2 read (from fourth location of command block) the bcrtmp transmits command word 2 to rt(a). the bcrtmp receives the rt status word from rt(a). status word dma for rt(a) status word dma arbitration status word write (to sixth location of command block) the bcrtmp receives the first data word data word dma (only if the bcrtmp is enabled to monitor the rt-to-rt message). dma arbitration data word write (starting at data list pointer address, incremented for each successive word) data word receptions and dmas continue until all data words are received. the bcrtmp receives the rt status word from rt(b). status word dma for rt(b) status word dma arbitration status word write (to seventh location of command block) exception handling. if an interrupting condition occurs during the message, the following occurs: for high-priority interrupts: hpint is asserted (if enabled in register 7). for message errors, the bcrtmp is put in a hold state until the interrupt is acknowledged (by writing a ?1? to the appropriate bit in register 8). for standard interrupts: dma arbitration (burst) interrupt status word write command block pointer write tail pointer read (into register 6) stdintp pulses low stdintl asserted (if enabled) processing continues
bcrtmp-41 if retries are enabled and a retry condition occurs, the following dma occurs: dma arbitration (burst) control word read command word 1 read (from third location of command block) data list pointer read the bcrtmp proceeds from the current command block to the next successive command block. if no message error has occurred during the current command block, the following occurs: dma arbitration (burst) command block tail pointer read (to determine location of next command block. note that this occurs only if no retry). dma hold cycle control word read (next command block) command word 1 read (next command block) data list pointer read if the bcrtmp detects a message error while processing the current command block, the following occurs: dma arbitration (burst) control word write command block tail pointer read (to determine location of next command block. note that this occurs only if no retry.) dma hold cycle control word read (next command block) command word 1 read (next command block) data list pointer read the bcrtmp proceeds again from point a, b, or c as shown above. 7.5 bc operational example (figure 19 on page 49) the bcrtmp is programmed initially to accomplish the following: the first command block is for a four-word rt-rt transfer with the bcrtmp monitoring the transfer and storing the data. auto-retry is enabled on the opposite bus using only one retry attempt, if the incoming status word is received with the message error bit set. wait for a time delay of 400ms before proceeding to the next command block. the data list pointer contains the address 0400h. the second command block is for a bc-rt transfer of two words. the end of list bit is set in its control word. the data list pointer contains the address 0404h. the polling enable bit is set and the polling compare register contains 0004h (check for subsystem fail bit. then: a. the cpu initializes all the appropriate registers and command blocks, and issues a start enable by writing a ?1? to register 0, bit 0. b. the bcrtmp, through executing a dma cycle, reads the control word, command words, and the data list pointer. the delay timer starts and message execution begins by transmitting the receive and transmit commands stored in the command blocks. the bcrtmp then waits to receive the status word back from the transmitting rt. c. the bcrtmp receives the rt status word with all status bits low from the transmitting rt and stores the status word in command block 1. the incoming data words from the transmitting rt follow. the bcrtmp stores them in memory locations 0400h - 0403h. if the status word indicates that the message cannot be transmitted (message error), the response time-out clock counts to zero and the allotted message time runs out. an auto-retry can be initiated if programmed to do so. nevertheless, the me bit in the control word is set. d. the bcrtmp receives the status word response from the receiving rt. the me bit in the status word is set, indicating the message is invalid. the bcrtmp initiates the auto retry function, (as programmed) on the alternate bus, re-transmits the command words, receives the correct status word, and stores the data again in locations 0400h - 0403h. this time the status word response from the receiving rt indicates the message transfer is successful. e. the timer delay between the two successive transactions counts down another 135 m s before proceeding. this is determined as follows: the message transaction time is approximately130 m s (the only approximation is due to the range in status response and intermessage gap times specified by
bcrtmp-42 mil-std-1553b). approximating that with the retry, the total duration for the two attempts is 265ms. f. the bcrtmp reads the tail pointer of command block 1 and places it in the current command register. it also reads the control word, command word, and data list pointer, and the first data word in the second command block. g. since this is a bc-rt transfer, the bcrtmp transmits the receive command followed by two data words from locations 0404h - 0405h in memory. the bcrtmp reads the second data word from memory while transmitting the first. h. the bcrtmp receives the status response from the rt. in this case, the status word indicates, by the me bit being low, that the message is valid. the status word also has the subsystem fail bit set. i. the status word is stored in the command block. the bcrtmp, having encountered the end of the list, halts message transactions and waits for another start signal. j. the bcrtmp asserts a high-priority interrupt indicating the end of the command list. due to the polling comparison failure, the bcrtmp also asserts a standard priority interrupt and logs the event in the interrupt log list. 8.0 m u l t i p l e p r o t o c o l o p t i o n s the ut1553 bcrtmp was developed from the industry?s first monolithic mil-std-1553b bus controller and remote terminal chip, the ut1553b bcrt. many additional features were added to the bcrt to create the ut1553 bcrtmp, which conforms to the requirements of the many different ?1553 standards? which developed between releases of mil-std-1553a and mil-std-1553b. user-configurable operational mode selections allow the bcrtmp to interface to a wide variety of 1553 protocols. protocols for which the user can configure the ut1553 bcrtmp include: mil-std-1553a, mil-std-1553b, mcdonnell douglas a3818, a5232, and a5690, and grumman aerospace sp-g-151a. the user need only to determine which operational mode settings are necessary to conform to the application?s needs. 8.1 operational modes the user can program the bcrtmp to conform to many of the currently used mil-std-1553 variations in protocol by simply selecting different operating modes. the bcrtmp provides seven mode select input pins and/or register bits t to select the different operating modes. if all mode bits are high, the bcrtmp operates in accordance with mil-std-1553b. 8.1.1 md0 (mode 0) legalization select (rt) the md0 input pin or bit 0 of register 14 selects the method of command legalization the bcrtmp uses. before issuing the appropriate rt response to a command, the bcrtmp must determine whether the command is legal. the bcrtmp accomplishes command legalization by one of two methods -- dma, by fetching the appropriate descriptor block (md0=1); or by using the legalization bus (md0=0). the legalization bus is the faster of the two methods and must be selected in order to meet the rt response time requirements of mil-std-1553a. since the bcrtmp cannot meet the ?a? response time unless it uses the legalization bus for command legalization, it forces mode 0 low internally if the ?a? response time is selected (md2=0). see also section 5.5, legalization bus. 8.1.2 md1 (mode 1) broadcast option select (bc, rt) the md1 input pin or bit 1 of register 14 selects the broadcast option the bcrtmp uses. the use of broadcast varies with differences in the 1553 protocols. for protocols that support the broadcast option (md1=1), the rt address 11111 is reserved to indicate a broadcast command. when the bus controller transmits a broadcast command, all rts must receive the message, but no rt is to respond with a status word. for protocols that do not support the broadcast option (md1=0), rt address 11111 is treated as a normal rt address. 8.1.3 md2 (mode 2) rt response time select (rt) the md2 input pin or bit 2 of register 14 selects the rt response time the bcrtmp uses in the rt mode to respond to 1553 commands. before an rt can respond to a command, it must determine whether that command is legal. as stated is section 8.1.1 above, the bcrtmp accomplishes command legalization by using either dma descriptor block fetching or by using the legalization bus. the rt response time differs among the 1553 protocols. the rt response time is measured from the zero crossing of the parity bit of the receive command?s last data word (or the zero crossing of the parity bit of the transmit command word) to the status word sync?s zero crossing. the maximum response time allowed for an rt is either 7.0 m s (?a? response time, md2=0) or 12.0 m s (?b? response time, md2=1), depending on the specification.
bcrtmp-43 8.1.4 md3 (mode 3) mode code option select (bc,rt) the md3 input pin or bit 3 of register 14 selects the mode code option the bcrtmp uses. differences in mode code definitions among the 1553 protocols concern the number of defined mode codes and whether mode codes with data are defined. mil-std-1553b?s definition is formal, but the other specifications define the possible mode codes to varying degrees, and may not use mode codes with data. the bcrtmp uses this selection to determine which bit patterns in the subaddress field of the command word indicate that the word count field contains a mode code. when md3 is high, either 00000 or 11111 in the subaddress field indicates a mode code. when md3 is low, only 00000 indicates a mode code. the bcrtmp provides additional control over mode code definition with the md6 selection (see section 8.1.7). also, the user can program bit 13 of register 14 to provide additional mode code control. 8.1.5 md4 (mode 4) status word option select (rt) the md4 input pin or bit 4 of register 14 selects the method the bcrtmp uses to generate the rt status word. most, if not all, 1553 protocols define the terminal address, message error (me), and terminal flag (tf) status word bits in the same manner. the remaining bits are defined in a variety of ways, not only dependent on the 1553 protocol, but also on the individual procurement specification. mil- std-1553b is quite formal in defining the status word bits, while the other specifications either define or leave undefined the other bits to varying degrees for procurement- specific options. when md4 is high, the bcrtmp generates the status word in accordance with mil-std- 1553b, using the contents of register 10 for many of the status bits. when md4 is low, the bcrtmp generates the status word using the programmable status register (register 15). see section 8.2.8 for more information regarding status word generation. 8.1.6 md5 (mode 5) message error technique select (rt) the md5 input pin or bit 5 of register 14 selects the method the bcrtmp uses for handling message errors. some 1553 protocols (e. g., mil-std-1553b) consider any message error reason to discard the entire message and suppress status word transmission, while others (e. g., mcdonnell douglas a3818) define the required activity according to message error severity. when md5 is high, message error handling is as described in mil-std-1553b. the mil-std-1553b definition states that on the occurrence of any message error condition, the rt sets the message error bit in the status word and suppresses status word transmission. message error conditions are defined as any of the following: parity errors, word count errors, or manchester errors. when md5 is low, message error handling is as described in mcdonnell douglas a3818. in this method, a less severe error (either a manchester error or a parity error in a data word, for example) requires special attention. the rt must mark the individual defective data word and respond with the message error bit set in the status word. when the bcrtmp detects this type of message error, the bcrtmp asserts the err output and places the word count for the defective data word on the least significant five bits of the legalization bus. due to the bcrtmp?s internal detection circuitry, errors in the first two data bits will force the bcrtmp to ignore the word and cause a word count error. word count errors cause the rt to suppress the status word and set the message error bit. 8.1.7 md6 (mode 6) mode code with data select (bc,rt) the md6 input pin or bit 6 of register 14 selects whether mode codes with data are allowed. when md6 is high, the mode codes defined in mil-std-1553b as mode codes with data have an associated data word. when md6 is low, the bcrtmp treats all mode codes as mode codes without data. 8.1.8 md7 (mode 7) remote terminal time out option select (bc,rt) the md7 input pin or bit 12 of register 0 selects the remote terminal time-out option. when md7 is high, the remote terminal time-out (rto) is nominally16 m s. when md7 is low, the remote terminal time-out (rto) is nominally 32 m s. 8.2 additional ut1553 bcrtmp features 8.2.1 domc do mode code control signal (rt) the bcrtmp provides additional mode code flexibility through use of the domc input. this input (internally pulled high) can be pulled low when the bcrtmp receives a mode code to prevent the bcrtmp from automatically executing the mode code. this input can be used to disable automatic execution of mode codes at any time; however, the individual selection of mode code execution applies only when using the legalization bus for command legalization (i.e., md0 is low), since the timing for mode code execution decision-making corresponds with mode code legalization using the legalization bus method only. if the user desires automatic execution of the mode code as defined in mil- std-1553b, then the user asserts the domc signal high after the bcrtmp receives the mode code. if the user desires to suppress automatic execution of the mode code, then the user asserts the domc signal low after the bcrtmp receives the mode code. the timing for the domc input follows, identically, the timing for the lglcmd of the legalization bus. see table 2 for the actions the bcrtmp takes when receiving specific mode codes.
bcrtmp-44 8.2.2 continuous wrap-around circuitry (bc,rt) the continuous wrap-around test feature is available for both bus controller and remote terminal operation. this feature permits continuous monitoring of the correct operation of the bcrtmp. the user either asserts the wrapen input low or writes a ?one? to bit 7 of register 14 to enable the continuous wrap- around feature. this feature permits the bcrtmp to compare everything it transmits with a ?reflected-back? version of the transmitted data. the data is reflected back by the 1553 transceiver and serially received into the bcrtmp?s decoder circuitry. if a mismatch is found between the transmitted data and the reflected data, then the bcrtmp asserts the wrapf output. asserting the wrapen and the altwrap inputs places the bcrtmp in a special off-line system diagnostics mode to allow the system to test both 1553 buses and the associated transceivers, transformers, connectors, etc. typical use of this feature would involve connecting a bus stub between the channel a and b connectors. the user could then place the bcrtmp in a bus controller mode of operation and execute a list of commands. with the altwrap and wrapen signals asserted, each transmission on the selected bus would be received through the wrap-around circuitry on the opposite bus. any assertion of the wrapf output would indicate that either the bcrtmp or some part of the bus or interface network has failed. note that if no rt is present in the system, then the bcrtmp will naturally detect a no-response error. this can be avoided by using broadcast commands, in which case no rt is expected to respond on the bus. 8.2.3 stop enable (bc,rt) the user implements this feature by setting bit 12 of register 14 high. in the bus controller mode, when this bit is high, the occurrence of any enabled interrupt (either standard or high-priority) causes the bcrtmp to automatically halt bus controller message processing. the bcrtmp resumes message processing when the user clears the interrupt by writing a ?one? to the appropriate bit in register 8. in the remote terminal mode, when this bit is high, the occurrence of any enabled interrupt (either standard or high-priority) causes the bcrtmp to automatically enter the forced busy mode of operation (see section 8.2.4). the bcrtmp exits the forced busy mode when the user clears the interrupt. 8.2.4 forced busy (rt) the user places the bcrtmp into the forced busy mode (rt only) by either pulling the fbusy input low or by writing a ?one? to bit 11 of register 15 or bit 9 of register 10. as discussed in section 8.2.3, the bcrtmp can also automatically enter the forced busy mode with the occurrence of enabled interrupts. while in the forced busy mode, all interrupts are disabled, the busy bit is set in the status word response, and no dma transactions will occur. the busyack output acknowledges that the bcrtmp is in the forced busy mode. 8.2.5 active signal (rt) the active output provides a means for the user to place the bcrtmp on the 1553 bus, enabled as an rt, and determines if it should assume bus mastership. the bcrtmp asserts the active signal when it detects a valid command on the bus to any rt address. the host determines which bus is active by examining bits 10 and 11 of register 14. to disable bus activity detection, the host writes a ?one? to bit 10 of register 14 to disable channel a (or bit 11 of register 14 for channel b). the active output remains deasserted until one or both of the channels is enabled. the user writes a ?zero? to the appropriate bit location(s) to enable the desired channel(s). performing a programmed or hardware reset also enables both activity monitors. 8.2.6 transmitter inhibit signals (bc,rt) the ut1553 bcrtmp contains two transmitter inhibit signals (one for channel a and one for channel b) that provide fail-safe timing for the 1553 buses. the signals are active ( timrona for channel a or timronb for channel b) when the bcrtmp begins transmitting and time out, or go inactive, 660 m s later, if the bcrtmp has not completed its transmission. 8.2.7 immediate clear mode the user sets bit 15 of register 15 to enter the immediate clear mode. when set, this bit will cause the bcrtmp to automatically clear all programmable status bits after the bcrtmp transmits the rt status word. when this bit is set, the first status word sent out contains the programmable status bits as programmed by either the programmable status register (?a? protocol, md4 = 0) or the rt address register (?b? protocol, md4 = 1). after status word transmission, all programmable status bits are cleared automatically. the exception to this occurs when the next command received is the transmit status word or transmit last command mode code. when either of these mode codes is received, the bcrtmp will respond with the appropriate status word from the previous valid command. this feature applies to all operational modes. 8.2.8 status word generation as a result of the differing requirements for status words in the various 1553 protocols, the bcrtmp must be capable of generating the rt status word in a variety of ways. it is appropriate to discuss the separate status word bits individually in order to understand how the bcrtmp generates these bits. the three status word bits defined as ?reserved? in mil-std-1553b are handled identically by the bcrtmp, as shown below. the action taken to generate
bcrtmp-45 all other status word bits varies, depending on the mode in which the bcrtmp is operating. in most cases, the bcrtmp generates the status word bits in different ways depending on the internal state of operational mode 4. 8.2.8.1 the terminal address field the terminal address field in the status word is always provided in the same manner. the bcrtmp uses pins rta4 to rta0 (or bits 4-0 of the remote terminal address register) to generate the remote terminal address bits of the status word. 8.2.8.2 the message error bit if md4 = 1, then the message error bit in the status word is set if any 1553 message error condition (or illegal command) occurs. if md4 = 0, then the message error bit in the status word is set when any 1553 message error condition (or illegal command) occurs or if bit 10 of register 15 is set. 8.2.8.3 the instrumentation bit if md4 = 1, then the bcrtmp uses bit 15 of register 10 to set the instrumentation bit in the status word. if md4 = 0, then the bcrtmp uses bit 9 of register 15 (the programmable status register) to set the instrumentation bit in the status word. 8.2.8.4 the service request bit if md4 = 1, then the bcrtmp uses bit 10 of register 10 to set the service request bit in the status word. if md4 = 0, then the bcrtmp uses bit 8 of register 15 (the programmable status register) to set the service request bit in the status word. also, the service request bit can be forced to reflect the complement of the status word busy bit (independent of the internal state of md4) if the user sets bit 12 of register 15 high. 8.2.8.5 the mil-std-1553b ?reserved? status word bits the bcrtmp always provides the mil-std-1553b ?reserved? status word bit field (bit times 12-14) in the status word in the same manner. the bcrtmp uses bits 5-7 of the register 15 to generate these bits (independent of the internal state of md4). 8.2.8.6 the broadcast command received bit if md4 = 1, then the broadcast command received bit in the status word is set when a broadcast command is received, if broadcast is enabled. if md4 = 0, then the broadcast command received bit in the status word is set if bit 4 of the programmable status register is set high. 8.2.8.7 the busy bit if md4 = 1, then the busy bit in the status word is set if either bit 14 of register 10 is set high or if the bcrtmp is in the forced busy mode (see section 8.2.4 for a discussion on entry to the forced busy mode). the assertion of the busy bit while in the forced busy mode can be disabled if both bits 13 and 14 of register 15 are set high. note that the forced busy mode is independent of the internal state of md4. if md4 = 0, then the busy bit in the status word is set if either bit 14 of register 10 or bit 3 of the programmable status register is set high, or if the bcrtmp is in the forced busy mode. 8.2.8.8 the subsystem flag bit if md4 = 1, then the subsystem flag bit in the status word is set either if the user sets bit 13 of register 10 or asserts the ssysf input of the bcrtmp, or if a bit failure has occurred. if md4 = 0, then the subsystem flag bit in the status word is set if the user sets bit 2 of the programmable status register. 8.2.8.9 the dynamic bus control acceptance bit if md4 = 1, the dynamic bus control acceptance bit in the status word will be set when the bcrtmp receives a dynamic bus control mode code that is not a broadcast command, if the user has not illegalized that command and has set bit 12 of register 10 high. 8.2.8.10 the terminal flag bit if md4 = 1, setting bit 11 of register 10 or the occurrence of a bit failure will always set the terminal flag bit in the status word. if md4 = 0, setting bit 0 of the programmable status register will always set the terminal flag bit in the status word. independent of the internal state of md4, the following conditions will also set the terminal flag bit in the status word. 1) if bit 13 of register 15 is ?1?, and bit 14 of register 15 is ?0?, then the terminal flag bit in the status word is also set if the busy bit or the subsystem flag bit is set in the status word. 2) if bit 13 of register 15 is ?0? and bit 14 of register 15 is ?1?, then the terminal flag bit in the status word is also set if any of the status word bits are set. note that if the terminal flag bit has been inhibited by mode code 6, this bit will not be set by any of the above methods.
bcrtmp-46 9.0 e x c e p t i o n h a n d l i n g a n d i n t e r r u p t l o g g i n g the exception handling scheme the bcrtmp uses is based on an interrupt structure and provides a high degree of flexibility in: defining the events that cause an interrupt, selecting between high-priority and standard interrupts, and selecting the amount of interrupt history retained. the interrupt structure consists of internal registers that enable interrupt generation, control bits in the rt and bc data structures (see the remote terminal descriptor definition section, page 30, and the bus controller command block definition, page 35), and an interrupt log list that sequentially stores an interrupt events record in system memory. the bcrtmp generates the interrupt log list (see figure 18) to allow the host cpu to view the standard interrupt occurrences in chronological order. each interrupt log list entry contains three words. the first, the interrupt status word, indicates the type of interrupt (entries are only for interrupts enabled). in the bc mode, the second word is a command block pointer that refers to the corresponding command block. in the rt mode, the second word is a descriptor pointer that refers to the corresponding subaddress descriptor. the cpu-initialized third word, a tail pointer, is read by the bcrtmp to determine the next interrupt log list address. the list length can be as long or as short as required. the configuration of the tail pointers determines the list length. the host cpu initializes the list by setting the tail pointers. this gives flexibility in the list capacity and the ability to link the list around noncontiguous blocks of memory. the host cpu sets the list?s starting address using the interrupt log list register. the bcrtmp then updates this register with the address of the next list entry.the internal high-priority interrupt status/reset register indicates the cause of a high- priority interrupt. the high-priority interrupt signal is reset by writing a ?1? to the set bits in this register. the interrupt structure also uses three bcrtmp- driven output signals to indicate when an interrupt event occurs: stdintl standard interrupt level. this signal is asserted when one or more of the events enabled in the standard interrupt enable register occurs. clear the signal by resetting the standard interrupt bit in the high-priority interrupt status/reset register. stdintp standard interrupt pulse. this signal is pulsed for each occurrence of an event enabled in the standard interrupt enable register. hpint high-priority interrupt. this signal is asserted for each occurrence of an event enabled in the high-priority interrupt/enable register. writing to the corresponding bit in the high-priority status/reset register resets it. figure 18. interrupt log list entry #3 entry #2 entry #1 tail pointer command block interrupt status pointer register interrupt log list pointer word subaddress/mode code descriptor pointer
bcrtmp-47 interrupt status word definition all bits in the interrupt status word are active high and have the following functions: bit number description bit 15 interrupt status word accessed. the bcrt always sets this bit during the dma write of the interrupt status word. if the cpu resets this bit after reading the interrupt status word, the bit can help the cpu determine which entries have been acknowledged. bit 14 no response time-out (message error condition). further defines the message error condition to indicate that a response time-out condition has occurred. bit 13 (rt) message error (me). indicates the me bit was set in the 1553 status word response. bits 12-8 reserved. bit 7 (rt) subaddress event or mode code with data word interrupt. indicates a descriptor control word has been accessed with either an interrupt upon valid command received bit set or an interrupt when index=0 bit set (and the index is decremented to 0). bit 6 (rt) mode code without data word interrupt. indicates a mode code has occurred with an interrupt when addressed interrupt enabled. bit 5 (rt) illegal broadcast command. applies to receive commands only. this bit indicates that a received command, due to an illegal mode code or subaddress field, has been received in the broadcast mode. this does not include invalid commands. bit 4 (rt) illegal command. this indicates that an illegal command has occurred due to an illegal mode code or subaddress and t/r field. this does not include invalid commands. bit 3 (bc) polling comparison match. indicates a polling comparison interrupt. bit 2 (bc) retry fail. indicates all the programmed retries have failed. bit 1 (bc, rt) message error. indicates a message error has occurred. bit 0 (bc) interrupt and continue. this corresponds to the interrupt and continue function described in the command block.
bcrtmp-48 table 2. bcrtmp automatic mode code execution t/r mode function automatic bit code execution 1 00000 dynamic bus control no 1 1 00001 synchronize (without data word) no 2 1 00010 transmit status word yes 1 00011 initiate self-test yes 1 00100 transmitter shutdown yes 1 00101 override transmitter shutdown yes 1 00110 inhibit terminal flag bit yes 1 00111 override inhibit terminal flag bit yes 1 01000 reset remote terminal yes 1 01001 reserved note 3 1 01010 reserved note 3 1 01011 reserved note 3 1 01100 reserved note 3 1 01101 reserved note 3 1 01110 reserved note 3 1 01111 reserved note 3 1 10000 transmit vector word yes 5 0 10001 synchronize (with data word) no 2 1 10010 transmit last command yes 1 10011 transmit bit word yes 0 10100 selected transmitter shutdown no 4 0 10101 override selected transmitter shutdown no 4 0 or 1 10110 reserved note 3 0 or 1 10111 reserved note 3 0 or 1 11000 reserved note 3 0 or 1 11001 reserved note 3 0 or 1 11010 reserved note 3 0 or 1 11011 reserved note 3 0 or 1 11100 reserved note 3 0 or 1 11101 reserved note 3 0 or 1 11110 reserved note 3 0 or 1 11111 reserved note 3 notes : 1. if the dynamic bus control enable bit in the rt address register (bit 12 of register 10) is set, then a high priority interrupt can occur (if enabled in register 7) and the dynamic bus control acceptance bit is set in the status word. 2. as with any subaddress or mode code, an interrupt can be caused and used for synchronization purposes. 3. these mode codes can be used, but the bcrtmp will not automatically execute them. the designer can enable an interrupt to occur on the reception of the mode code. 4. the host cpu is responsible for shutting down a bus in a more than dual-redundant system. 5. for the transmit vector word mode code, the bcrtmp must access memory for the vector word, as with other mode codes with data (except mode codes 18 and 19).
bcrtmp-49 f i g u r e 1 9 . b u s c o n t r o l l e r s c e n a r i o r t i 2 r t i 2 r t i 2 r t i 2 * * * * s t a t u s d a t a 4 d a t a 3 d a t a 2 d a t a 1 s t a t u s c m d # 2 c m d # 1 r t i 2 r t i 1 b c b c s t a t u s d a t a 4 d a t a 3 d a t a 2 d a t a 1 s t a t u s c m d # 2 c m d # 1 r t i 2 r t i 1 b c b c m a n c h e s t e r d a t a b u s a m a n c h e s t e r d a t a b u s b i n t e r r u p t a c t i v i t y b c r t m p a c t i v i t y d e s c r i p t i o n r t i 2 r t i 2 r t i 2 r t i 2 b c r t m p d m a a u t o r e t r y d e s c r i p t i o n a c t i v i t y b c r t m p a c t i v i t y b c r t m p d m a i n t e r r u p t d a t a b u s b m a n c h e s t e r d a t a b u s a m a n c h e s t e r b c r t i b c b c c m d d a t a 1 d a t a 2 s t a t u s * time out to 400 s fetch tail pointer store status word #2 store data word#4 store data word #3 store data word#2 store data word#1 store status word #1 fetch command word #2 fetch data pointer fetch command word #1 fetch control word read log list tail ptr store cmd blockptr store interrupt status word recognize me bit store status word #2 store data word#4 store data word#3 store data word #2 store data word#1 store status word #1 fetch command word #2 fetch data pointer fetch command word #1 fetch control word start bcrtmp initialize registers so stop bcrtmp eol in control word store interrupt status word fetch data word #2 fetch data word#1 fetch data pointer fetch command word fetch control word time out to 400 s m n o t e s : 1 . t i m e s f o r d m a a r b i t r a t i o n a n d b c r t m p d m a a c t i v i t i e s a r e n o t s h o w n t o s c a l e r e l a t i v e t o t h e 1 5 5 3 b m e s s a g e w o r d l e n g t h s . t h i s i s d o n e t o i l l u s t r a t e t h e o p e r a t i o n o f t h e s e s i g n a l s . 2 . * = r e s p o n s e t i m e o f 4 t o 1 2 m s . 3 . d m a a r b i t r a t i o n r e p r e s e n t s t h e d m a r t o d m a c k - s e q u e n c e . 4 . t h e s c e n a r i o a s s u m e s t h a t a l l d m a g r a n t s ( d m a g ) a r e r e c e i v e d i n t h e r e q u i r e d p e r i o d o f t i m e . 0 m s 1 6 8 t o 1 7 5 t o 4 8 4 t o 4 9 2 m s 4 0 0 m s 3 4 4 t o 3 9 2 m s 4 0 0 m s b c r t m p d m a a r b i t r a t i o n 3 b c r t m p d m a a r b i t r a t i o n 3 m
bcrtmp-50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 1 5 5 1 reserved remote terminal address sync status word data word sync sync data p p remote terminal address t/r subaddress/ mode data word count/mode code bit times command word m e s s a g e e r r o r i n s t r u m e n t a t i o n s e r v i c e r e q u e s t b r o a d c a s t c o m m a n d r e c e i v e d b u s y s u b s y s t e m f l a g d y n a m i c b u s c o n t r o l a c c e p t a n c e t e r m i n a l f l a g p a r i t y note: t/r - transmit/receive p - parity figure 20. mil-std-1553b word formats
bcrtmp-51 10.0 o p e r a t i n g c o n d i t i o n s * (r e f e r e n c e d t o v s s ) 11.0 dc e l e c t r i c a l recommended operating conditions symbol parameter limits unit dc supply voltage temperature range v c operating frequency mhz t c f o v dd 12 .01% 4.5 to 5.5 -55 to +125 symbol parameter limits unit dc supply voltage voltage on any pin dc input current storage temperature v v ma c notes: maximum junction temperature c mw 1. does not reflect the added p d due to an output short-circuited. * stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods may affect device reliability. q thermal resistance, junctionx0106to-case c/watt v dd v i/o v i t stg t jmax p d jc average power dissipation 1 -0.3 to + 7.0 -0.3 to v dd + 0.3 10 -65 to + 150 + 175 300 12
bcrtmp-52 11.0 dc e l e c t r i c a l c h a r a c t e r i s t i c s (vdd = 5.0v 10%; -55 c < tc < + 125 c) notes : 1. supplied as a design limit, but not guaranteed or tested. 2. not more than one output may be shorted at a time for a maximum duration of one second. 3. measured only for initial qualification, and after process or design changes which may affect input/output capacitance. 4. includes current through input pull-up. instantaneous surge currents on the order of 1 ampere can occur during output switching. voltage supply should be adequately sized and decoupled to handle a large current surge. 5. all inputs with internal pull-ups should be left floating. all other inputs should be tied high or low. 6. functional tests are conducted in accordance with mil-std-883 with the following input test conditions v ih = v ih (min) +20%, -0%; v il = v il (max) +0%, -50%, as specified herein, for ttl-compatible inputs. devices may be tested using input voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 7. to 1.0e6 total dose; above this level, cmos i/os required. symbol parameter condition minimum maximum unit v il rad and non-rad low-level input voltage ttl inputs cmos inputs 0.8 .3 v dd v v v ih non-rad high-level input voltage ttl inputs cmos inputs 2.0 .7 v dd v v v ih rad-hard high-level input voltage 6 ttl inputs 7 cmos inputs 2.2 .7 v dd v v i in non-rad input leakage current ttl inputs inputs with pull-up resistors inputs with pull-up resistors v in = v dd or v ss v in = v dd v in = v ss -1 -1 -550 -1 -1 -80 ma ma ma i in rad-hard input leakage current ttl 7 , cmos inputs inputs with pull-up resistors inputs with pull-up resistors v in = v dd or v ss v in = v dd v in = v ss -10 150 -900 10 900 -150 ma ma ma v ol low-level output voltage ttl outputs cmos outputs i ol = 3.2ma i ol = 50ma 0.4 v ss + .1 v v v oh high-level output voltage ttl outputs cmos outputs i oh = -400ma i oh = -50ma 2.4 v dd - .1 v v i oz three-state output leakage current ttl outputs v o = v dd or v ss -10 10 ma i os short-circuit output current 1, 2 v dd = 5.5v, v o = v dd v dd = 5.5v, v o = 0v -100 100 ma ma c in input capacitance 3 | = 1mhz @ 0v 10 pf c out output capacitance 3 | = 1mhz @ 0v 15 pf c io bidirect i/o capacitance 3 | = 1mhz @ 0v 20 pf i dd average operating current 1, 4 | = 12mhz, c l = 50pf 50 ma qi dd quiescent current see note 5 3 ma
bcrtmp-53 12.0 ac e l e c t r i c a l c h a r a c t e r i s t i c s (o v e r r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ) parameter symbol bus output out-of-phase output in-phase input notes: 1. timing measurements made at (v ih min + v il max)/2. 2. timing measurements made at (v ol max + v oh min)/2. 3. based on 50pf load. 4. unless otherwise noted, all ac electrical characteristics are guaranteed by design or characterization. 1 1 2 2 2 2 v ih v il max v ih min v il max v oh min v ol max v oh min v ol max v oh min v ol max t a t b t c t d t e t f t g t h t a t b t c t d t e t f t g t h input - to response - input to response input - to response input to response - input to data valid input to high z input - to high z input - to data valid 90% figure 22. ac test loads and input waveforms note : input pulses 10% 10% 90% < 2ns < 2ns 50pf 3v 0v 5v ? i ref (source) i ref (sink) v ref output loading figure 21. typical timing measurements
bcrtmp-54 mclkd2 address data aen burst dma grant recognized on this edge thmc1+10 40 symbol parameter min max units 0 thmc1-10 mclk-20 ns ns ns ns ns ns 0 0 2xmclk mclk m 45 4xmclk 6xmclk mclk+20 3.5 (1.9) notes: 0 ns 10 s 0 1.9 (0.8) m s ns 0 10 t shl1 t phl1 1 t phl2 t pzl1 t hlh2 t phl3 t pw2 t oozl1 t phl4 t phl4 t shl1 t pw2 t oozl1 t phl4 t phl1 t phl2 t phl3 t pzl1 t hlh2 dmack to dmar high impedance dmag to dmack 3 dmag to tsctl rwr / rrd - to dmack high impedance tsctl to rwr/rrd dmag to dmag - dmar to burst - dmar to dmag 4,6 tsctl to address valid dmar dmag dmack tsctl memcso rwr/ rrd 2 1. guaranteed by test. 2. see figures 24 and 25 for detailed dma read and write timing. 3 dmag must be asserted at least 45ns prior to the rising edge of mclkd2 in order to be recognized for the next mclkd2 cycle. if dmag is not asserted at least 45ns prior to the rising edge of mclkd2, dmag is not recognized until the following mclkd2 cycle. 4. provided mclk = 12mhz. number in parentheses indicates the longest dmar to dmag allowed during worst-case bus switching conditions in order to meet mil-std-1553b rt response time. the number not in parentheses applies to all other circumstances. 5 provided mclk = 6mhz. number in parentheses indicates the longest dmar to dmag allowed during worst-case bus switching conditions in order to meet mil-std-1553b rt response time. the number not in parentheses applies to all other circumstances. 6. the maximum limit for this specification applies only when using dma legalization (md0=1) mclk = period of the memory clock cycle. burst signal is for multiple-word dma accesses. thmc1 is equivalent to the positive phase of mclk (see figure 24). dmar to dmag 5,6 figure 23. burst dma timing
bcrtmp-55 ns ns ns ns ns ns ns 40 - - thmc1 mclk+5 thmc2 0 40 5 thmc1-10 mclk-5 thmc2-20 units max min parameter symbol data address mclkd2 mclk thmc1 thmc2 ns 60 0 40 0 t shl1 t pw1 t hlz2 t hlz1 t slh1 t plh2 t iohl1 1 t plh1 1 t plh1 t iohl1 t plh2 t shl1 t slh1 t pw1 t hlz1 t hlz2 address valid to rrd (address setup) rrd to rrd - rrd - to address high impedance (address hold) rrd - to data high impedance (data hold) data valid to rrd - (data setup) mclk - to mclkd2 - mclk - to tsctl / memcso mclk - to rrd tsctl memcso rrd note: 1. guaranteed by test. figure 24. bcrtmp dma read timing (one-word read)
bcrtmp-56 ns ns ns ns ns ns ns 40 0 mclk-5 thmc1-20 thmc1-20 0 thmc2-20 (address hold) (address setup) units max min parameter symbol data address mclkd2 mclk thmc2 30 thmc1 thmc1 mclk+5 thmc1 thmc2 ns 60 0 1. guaranteed by test. note: 40 0 t shl1 t pw1 t hlz2 t hlz1 t oozl1 1 t plh2 t iohl1 1 t plh1 1 address valid to rwr rwr to data valid rwr - to address high impedance rwr - to data high impedance mclk - to mclkd2 - mclk - to tsctl / memcso mclk - to rwr rwr to rwr - (data hold) tsctl memcso rwr t plh1 t iohl1 t plh2 t shl1 t oozl1 t pw1 t hlz1 t hlz2 figure 25. bcrtmp dma write timing (one-word write)
bcrtmp-57 ns ns ns ns ns ns 5 5 - (data hold) (address hold) units max min parameter symbol address data (data access) 60 80 80 - - - 60 50 - notes: 1. guaranteed by test. 2. user must adhere to both t oozh1 and t oozh2 timing constraints to ensure valid data. t hlh2 rd + cs - to data high impedance t oozh2 t oozh1 1 t hlh1 t pw1 t pw2 address valid to data valid rd + cs to data valid rd + cs - to address high impedance rd + cs to rd + cs - rd + cs - to rd + cs rd + cs t oozh2 t oozh1 t hlh1 t hlh2 t pw1 t pw2 10 10 60 60 - - ns ns ns ns ns ns (data hold) (address hold) (address setup) units max min parameter symbol address data (data setup) 60 80 - - - - t hlh2 wr + cs - to address high impedance t pw2 wr + cs - to wr + cs t hlh1 wr + cs - to data high impedance t pw1 wr + cs to wr + cs - t slh1 data valid to wr + cs - t shl1 address valid to wr + cs wr + cs t shl1 t pw1 t hlh2 t hlh1 t slh1 t pw2 figure 26. bcrtmp register read timing figure 27. bcrtmp register write timing
bcrtmp-58 0 symbol parameter min max units manchester dma activity c d d data word to dma activity 4 m s note: the pulsewidth = (11ms -t dma -t pzl1 ) where t dma is the time to complete dma activity (i.e., dmar to dmack - ). t pzl1 t pz this diagram indicates the relationship between the incoming manchester code and dma activity (i.e., dmar to dmack - ). ns ns units max min parameter symbol 0 0 0 ns 30 30 30 note: 1. guaranteed by test. t plh1 1 rd to rrd t plh2 1 t plh3 1 wr to rwr memcsi to memcso t plh1 t plh2 t plh3 rrd rd wr rwr memcsi memcso figure 28. bcrtmp dual-port interface timing delays figure 29. dma activity(rt mode)
bcrtmp-59 40 30 10 ns ns units max min parameter symbol 0 0 0 ns mclk mclkd2 notes : 1. guaranteed by test. 2. when dmag is asserted before dmar , the dmag signal passes through the bcrtmp as dmago . t plh2 1 dmag to dmago t shl1 t phl1 dmack to dmar high impedance mclk - to mclkd2 - dmar dmag dmago dmack t plh2 t phl1 t shl1 figure 30. bcrtmp arbitration when dmag is asserted before arbitration figure 27. bcrtmp register writetiming
bcrtmp-60 figure 31. bcrtmp legalization bus timing ns ns ns ns 750 200 100 0 lglcmd lgl0-10 ns 450 legalization bus valid to lglcmd| (setup time) symbol parameter min max units (pulse width) (setup time) (hold time) lglen to lglen - t pw1 lglen t hlh1 t slh1 t hlz1 t hlh2 lglen to legalization bus valid lglcmd - to lglen - lglen - to lglcmd invalid t pw1 t hlh2 t hlz1 t hlh1 t slh1
bcrtmp-61 3xmclk-10 5xmclk 10xmclk+1 340 1 8xmclk+0.5 320 - ns ns units max min parameter symbol burst ns s m tsctl - to stdintp / stdintl t oolh1 stdintp to stdintp - t pw1 dmack to rwr t oohl1 dmag to stdintl t oohl2 dmar dmag dmack rwr rrd tsctl stdintl stdintp t oolh1 t oohl1 t oohl2 t pw1 note: address and data bus relationships (not shown) are identical to figure 23. figure 32. bcrtmp interrupt log list entry operation timing
bcrtmp-62 md2 md3 md4 md5 md6 md7 a0 a1 a2 a3 a4 a5 a6 a7 nc vss vdd nc a8 a9 a10 a11 a12 a13 a14 a15 rta0 rta1 rta2 rta3 rta4 rtpt rao lgl5 lgl4 lgl3 lgl2 lgl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 nc vdd vss nc d6 d5 d4 d3 d2 d1 d0 comstr cha/b extovr bcrtsel timronb timrona hpint 1 18 116 50 84 lgl1 33 34 132 66 67 99 100 figure 33a. bcrtmp flatpack identification (top view) r a z t a o t a z r b o r b z t b o t b z m c l k t e s t a e n c s r d m e m c s i n c v v n c m e m c s o r r d r w r d m a r d m a g m c l k d 2 d m a c k t s c t l b u r s t d m a g o f b u s y b u s y a c k a c t i v e s t d i n t l s t d i n t p l g l 6 l g l 7 l g l 8 l g l 9 l g l 1 0 b r d c a s t m c e r r l g l c m d d o m c l g l e n s s y s f b c r t f n c n c v v n c c l k a l t w r a p w r a p f w r a p e n m r s t m d o 0 m d o 1 m d o 2 m d o 3 m d o 4 m d o 5 m d o 6 l o c k m d 0 m d 1 s s d d s s d d w r 13.0 p a c k a g e o u t l i n e d r a w i n g s
bcrtmp-63 n1 - mdo2 n2 - mdo5 n3 - md0 n4 - nc n5 - md4 n6 - a0 n7 - a3 n8 - v ss n9 - v dd n10 - a12 n11 - rta1 n12 - rta4 n13 - rtpty n14 - raz n15 - rbo a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 figure 33b. bcrtmp pingrid array pin identification (bottom view) a1 - nc a2 - lgl2 a3 - d14 a4 - d13 a5 - d12 a6 - d8 a7 - d7 a8 - d6 a9 - d4 a10 - d3 a11 - nc a12 - cha/ b a13 - bcrtsel a14 - nc a15 - nc b1 - nc b2 - lgl5 b3 - lgl1 b4 - d15 b5 - nc b6 - d10 b7 - d9 b8 - d5 b9 - d1 b10 - d0 b11 - extovr b12 - timrona b13 - hpint b14 - stdintp b15 - busyack p1 - mdo6 p2 - md1 p3 - md2 p4 - md3 p5 - md6 p6 - a1 p7 - a2 p8 - a6 p9 - a10 p10 - a11 p11 - nc p12 - rta0 p13 - rta2 p14 - rao p15 - nc c1 - lgl9 c2 - lgl6 c3 - lgl4 c4 - lgl3 c5 - lgl0 c6 - d11 c7 - v dd c8 - v ss c9 - d2 c10 - comstr c11 - timronb c12 - nc c13 - stdintl c14 - fbusy c15 - tsctl r1 - nc r2 - nc r3 - md5 r4 - md7 r5 - nc r6 - a4 r7 - a5 r8 - a7 r9 - a8 r10 - a9 r11 - a13 r12 - a14 r13 - a15 r14 - rta3 r15 - nc d1 - brdcast d2 - lgl7 d3 - nc d4 - nc d13 - active d14 - burst d15 - dmack e1 - nc e2 - lgl10 e3 - lgl8 e13 - dmago e14 - nc e15 - mclkd2 f1 - lglen f2 - lglcmd f3 - mc f13 - dmag f14 - dmar f15 - rrd g1 - ssysf g2 - err g3 - domc g13 - v dd g14 - rwr g15 - memcso h1 - nc h2 - bcrtf h3 - v dd h13 - v ss h14 - wr h15 - memcsi j1 - clk j2 - wrapf j3 - v ss j13 - aen j14 - test j15 - rd k1 - altwrap k2 - wrapen k3 - mrst k13 - tbz k14 - mclk k15 - cs l1 - mdo0 l2 - nc l3 - mdo4 l13 - taz l14 - rbz l15 - nc m1 - mdo1 m2 - mdo3 m3 - lock m13 - nc m14 - tao m15 - tbo registration
packaging -1 package selection guide note: 1. 84lcc package is not available radiation-hardened. product rti rtmp rtr bcrt bcrtm bcrtmp rts xcvr 24-pin dip (single cavity) x 36-pin dip (dual cavity) x 68-pin pga x x 84-pin pga x x x x 1 144-pin pga x 84-lead lcc x x x 1 36-lead fp (dual cavity) (50-mil ctr) x 84-lead fp x x 132-lead fp x x
packaging-2 1 144-pin pingrid array e 1.565 0.025 -b- d 1.565 0.025 -a- 0.080 ref. (2 places) 0.040 ref. 0.100 ref. (4 places) a 0.130 max. q 0.050 0.010 a a l 0.130 0.010 pin 1 i.d. (geometry optional) -c- (base plane) b 0.018 0.002 0.030 0.010 c a b c side view top view 0.003 min. typ. d1/e1 1.400 0.100 typ. e pin 1 i.d. (geometry optional) 2 r p n m l k j h g f e d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 notes: 1. true position applies to pins at base plane (datum c). 2. true position applies at pin tips. 3. all package finishes are per mil-m-38510. 4. letter designations are for cross-reference to mil-m-38510. bottom view
packaging -3 132-lead flatpack (25-mil lead spacing) side view top view bottom view a-a detail a 0.018 max. ref. 0.014 max. ref. (at braze pads) l 0.250 min. ref. lead kovar see detail a a a c 0.005 + 0.002 - 0.001 a 0.110 0.006 d1/e1 0.950 0.015 sq. d/e 1.525 0.015 sq. pin 1 i.d. (geometry optional) e 0.025 notes: 1. all package finishes are per mil-m-38510. 2. letter designations are for cross-reference to mil-m-38510. s1 0.005 min. typ.
packaging-4 84- lcc side view top view bottom view a-a notes: 1. all package finishes are per mil-m-38510. 2. letter designations are for cross-reference to mil-m-38510. l/l1 0.050 0.005 typ. b1 0.025 0.003 e 0.050 e1 0.015 min. pin 1 i.d. (geometry optional) j 0.020 x 455 ref. h 0.040 x 45_ ref. (3 places) d/e 1.150 0.015 sq. a 0.115 max. a1 0.080 0.008 a a pin 1 i.d. (geometry optional)
packaging -5 84-lead flatpack (50-mil lead spacing) side view top view bottom view a-a d/e 1.810 0.015 sq. notes: 1. all package finishes are per mil-m-38510. 2. letter designations are for cross-reference to mil-m-38510. detail a d1/e1 1.150 0.012 sq. a 0.110 0.060 a a c 0.007 0.001 lead kovar see detail a pin 1 i.d. (geometry optional) b 0.016 0.002 l 0.260 min. ref. s1 0.005 min. typ. 0.050 e 0.014 max. ref. (at braze pads) 0.018 max. ref.
packaging-6 84-pin pingrid array side view top view bottom view a-a d 1.100 0.020 e 1.100 0.020 -b- -a- a 0.130 max. q 0.050 0.010 l 0.130 0.010 a a -c- (base plane) b 0.018 0.002 pin 1 i.d. (geometry optional) 1.000 d1/ e 0.100 typ. 0.003 min. l k j h g f e d 1 2 3 4 5 6 7 8 9 10 11 notes: 1. true position applies to pins at base plane (datum c). 2. true position applies at pin tips. 3. all packages finishes are per mil-m-38510. 4. letter designations are for cross-reference to mil-m-38510. pin 1 i.d. (geometry optional) 1 0.030 0.010 c a b c 2
packaging -7 side view top bottom view a-a d 1.100 0.020 pin 1 i.d. (geometry optional) l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 notes: 1 true position applies to pins at base plane (datum c). 2 true position applies at pin tips. 3. all packages finishes are per mil-m-38510. 4. letter designations are for cross-reference to mil-m-38510. pin 1 i.d. (geometry optional) d1/e1 1.00 0.003 min. typ. e 0.100 typ. a 0.130 max. q 0.050 0.010 l 0.130 0.010 a a -a- -b- e 1.100 0.020 -c- (base plane) 68-pin pingrid array 0.030 0.010 c a b 1 2 c ? ? b 0.010 0.002
packaging-8 d 1.800 0.025 36-lead flatpack, dual cavity (100-mil lead spacing) top view end view e 0.750 0.015 notes: 1 all package finishes are per mil-m-38510. 2. it is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. a thermally conductive material such as mereco xln-589 or equivalent should be used. 3. letter designations are for cross-reference to mil-m-38510. pin 1 i.d. (geometry optional) l 0.490 min. b 0.015 0.002 e 0.10 c 0.008 + 0.002 - 0.001 q 0.080 0.010 (at ceramic body) a 0.130 max.
packaging -9 36-lead flatpack, dual cavity (50-mil lead spacing) top e 0.700 + 0.015 notes: 1. all package finishes are per mil-m-38510. 2. it is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. a thermally conductive material such as mereco xln-589 or equivalent should be used. 3. letter designations are for cross-reference to mil-m-38510. c 0.007 + 0.002 - 0.001 q 0.070 + 0.010 (at ceramic body) a 0.100 max. end d 1.000 0.025 b 0.016 + 0.002 e 0.050 pin 1 i.d (geometry optional) l 0.330 min.
packaging-10 36-lead side-brazed dip, dual cavity top view end view e 0.590 0.012 notes: 1. all package finishes are per mil-m-38510. 2. it is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. a thermally conductive material such as mereco xln-589 or equivalent should be used. 3. letter designations are for cross-reference to mil-m-38510. pin 1 i.d. (geometry optional) side view s1 0.005 min. d 1.800 0.025 s2 0.005 max. e 0.100 a 0.155 max. l/l1 0.150 min. c 0.010 + 0.002 - 0.001 e1 0.600 + 0.010 (at seating plane) b 0.018 0.002
ordering information ut1553b bcrtmp bus controller remote terminal multi-protocol: s lead finish: (a) = solder (c) = gold (x) = optional case outline: (x) = 144 pin pga (y) = 132 pin fp class designator: (-) = blank or no field is qml q drawing number: 8950101 total dose: (-) = none federal stock class designator: no options 5962 * * * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an "x" is specified when ordering, part marking will match the lead finish and will be either "a" (solder) or "c" (gold). 3. 132 fp available with gold lead finish only. 4. for qml q product, the q designator is intentionally left blank in the smd number (e.g. 5962-8950101yc).
ut1553b bcrtmp bus controller remote terminal multi-protocol lead finish: (a) = solder (c) = gold (x) = optional screening: (c) = military temperature (p) = prototype package type: (g) = 144 pin pga (w) = 132 pin fpv (gold only) utmc core part number ut1553b bcrtmp - * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an "x" is specified when ordering, part marking will match the lead finish and will be either "a" (solder) or "c" (gold). 3. mil temp range flow per utmc?s manufacturing flows document. devices are tested at -55 c , room temperature, and 125 c . radiation neither tested nor guaranteed. 4. prototpe flow per utmc?s document manufacturing flows and are tested at 25 c only. radiation characteristics neither tested nor guaranteed. lead finish is gold except for lcc 5. 132 fp available with gold lead only.
packaging -11 e 0.590 0.015 s1 0.005 min. s2 0.005 max. top view pin 1 i.d. (geometry optional) d 1.200 0.025 side view a 0.140 max. l/l1 0.150 min. 0.100 e notes: 1. all package finishes are per mil-m-38510. 2. it is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. a thermally conductive material such as mereco xln-589 or equivalent should be used. 3. letter designations are for cross-reference to mil-m-38510. end view c 0.010 + 0.002 - 0.001 e1 0.600 + 0.010 (at seating plane) b 0.018 0.002 24-lead side-brazed dip, single cavity
ordering information ut1553b bcrtmp bus controller remote terminal multi-protocol: s lead finish: (a) = solder (c) = gold (x) = optional case outline: (x) = 144 pin pga (y) = 132 pin fp class designator: (-) = blank or no field is qml q drawing number: 8950101 total dose: (-) = none federal stock class designator: no options 5962 * * * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an "x" is specified when ordering, part marking will match the lead finish and will be either "a" (solder) or "c" (gold). 3. 132 fp available with gold lead finish only. 4. for qml q product, the q designator is intentionally left blank in the smd number (e.g. 5962-8950101yc).
ut1553b bcrtmp bus controller remote terminal multi-protocol lead finish: (a) = solder (c) = gold (x) = optional screening: (c) = military temperature (p) = prototype package type: (g) = 144 pin pga (w) = 132 pin fpv (gold only) utmc core part number ut1553b bcrtmp - * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an "x" is specified when ordering, part marking will match the lead finish and will be either "a" (solder) or "c" (gold). 3. mil temp range flow per utmc?s manufacturing flows document. devices are tested at -55 c , room temperature, and 125 c . radiation neither tested nor guaranteed. 4. prototpe flow per utmc?s document manufacturing flows and are tested at 25 c only. radiation characteristics neither tested nor guaranteed. lead finish is gold except for lcc 5. 132 fp available with gold lead only.

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